"This article describes the sigma-delta encoded data to demodulate the sigma-delta encoded data in the motor control application. Then, different methods of SINC filter and control algorithm synchronization are discussed in detail.
Motor driver manufacturers continue to improve their performance and robustness. Some improvements are achieved by using more advanced control algorithms and higher computing power. Other improvements are implemented by minimizing the non-ideal effects in the feedback circuit, such as delay, inclinement, and temperature drift.
For the feedback of the motor control algorithm, the most critical part is the measurement of the phase current. As the control performance is improved, the system has a non-ideal effect such as timing accuracy, offset / gain error, and multi-feedback channels. Over the years, semiconductor companies have been committed to reducing these non-ideal effects in the feedback signal chain, and this trend is likely to continue. The ADUM7701 is an example of the latest generation isolation σ-ΔADC optimized for measuring phase currents. Although the performance of ADC is important, it is also likely to cause non-ideal effects in the rest of the feedback path. This article does not consider the ADC, mainly discusses the rest of the feedback path. Although this paper focuses on motor control applications, it also applies to any other system that requires σ-ΔADC.
Typical signal chains when using σ-ΔADC, as shown in Figure 1. The analog input voltage is generated by allowing the phase current through a resistive shunt. Σ-ΔADC converts an analog signal to a 1-bit data stream and provides electrical isolation, so that everything after the ADC is isolated from the motor phase potential. After the converter is the demodulation executed by the filter. This filter converts 1 bit signal to a multi-bit (m bit) signal and reduces data update rate by extracting process. Although the filter draws reduces the data rate, the rate is usually too high, and the update rate of the control algorithm cannot be matched. In order to solve this problem, we increase the final down-descending stage.
Figure 1. A sigma-delta signal chain for measuring the phase current.
This article assumes that the filter and extracted stage are implemented in the FPGA, and the filter is a three-order SINC filter (SINC3)
SINC filter synchronization
The defect of sigma-ΔADC and SINC filters is that it is difficult to control in the same time domain and lack the specified sampling time. Both filters have some worrying places compared to traditional ADCs with dedicated sampling maintenance circuits. However, there is also a way to solve this problem. As indicated in this section, synchronize the SINC filter and the rest of the system and is critical to sampling phase current at the appropriate time. If this is not possible, the measurement will be significantly distorted.
The output of the SINC filter does not represent the input of this time σ-ΔADC. Instead, the output is a weighted average input during the past window. This is caused by the pulse of the filter. Figure 2A shows the pulse response of SINC3 when the draw ratio is 5. As can be seen from the figure, the filter output is the weighting of the input sequence, and the intermediate sampling obtains large weight, and the sampling weight at the start / end of the sequence is low.
Several basic definitions need to be given before continuing to discuss. The σ-Δadc clock, also known as the modulator clock, is represented as FMOD. The extraction rate (DR) determines the extraction frequency (FDEC) and is associated with FMOD, as shown in Equation 1:
Figure 2 shows the impact of the impulse response filter step response. When applying this step, the filter output is not affected, and the filter reaches a stable state after 3 complete extraction cycles. Therefore, some important features of the SINC3 filter can be expressed as:
Group delay is 1.5 extraction cycles
Establishment time is 3 extraction cycles
These properties are very important when the filter is synchronized with the control system, and this article will always be used.
Figure 2. (a) SINC filter pulse response of 5 filter extraction rate. (b) The step response of the SINC filter and the relationship with the pulse response.
You must define the characteristics of the input signal before discussing the SINC filter synchronization. This reverses the synchronization characteristics of the filter.
Figure 3 shows an analog phase current of a 3-phase permanent magnet motor driven by a voltage source inverter. The modulation mode is the space vector PWM, the switching frequency is 10kHz. Load the motor to a 5A peak phase current and 3000 rpm speed. This setting plus 3 polar logs, which can obtain 6.67 ms electrical basic cycle.
Figure 3. Motor phase current at the time of spatial vector pulse width modulation.
Phase current can be constructed as two components: average component and switching components. For control purposes, only the average component of the current is only, so the switching components must be completely removed. To extract average components, the most common method is to sample signals (for motor terminals) synchronized with the PWM. As shown in Figure 4. The uppermost signal displays the switch waveform of the phase current, and the intermediate signal displays the high-end PWM of the corresponding inverter phase arm, and the lowermost signal displays the synchronization signal from the PWM timer. The PWM synchronization signal is set in the start and intermediate of the PWM cycle. For the sake of concise, it is assumed that all three-phase duty cycle is 50%, which means that the current has only one rising slope and a falling slope. At the rising edge of the PWM synchronization signal, the current takes the average, so if the current is sampling at that moment, the switching component will be completely suppressed. In fact, the sampling hold circuit corresponds to a filter having an infinite attenuation on the switching frequency.
Figure 4. Measuring the phase current at the starting point and the central point at the starting point and central point of the PWM period.
Figure 5 shows the result of using such sampling to the waveform shown in Figure 3. The right side is the waveform enlargement of the actual phase current and sampling current. Note how the sample hold process completely eliminates ripple.
Figure 5. Ideal Phase Electric Sampling: (a) The Ideal Sampling Current Base Wave Cycle, (B) The waveform enlargement of the phase current and the sampling current current.
The sampling current is represented per unit, where 0A is mapped to 0.5, and the total proportion value is 8A. This ratio is to be more easier to compare with the rear sigma-delta measurement. The results shown in Figure 5 are ideal scenes, only the fundamental component remains after sampling. Therefore, this data can be used as a reference value for comparing the σ-Δ measure value.
Σ-Δ measurement and mixing
In the ideal sampling keep the ADC, the fundamental component can be extracted due to strict control of the sampling time. However, sigma-delta conversion is a continuous sampling process, and the ripple component will inevitably become part of the measurement.
In σ-Δ conversion, the extraction rate is closely related to the signal-to-noise ratio (SNR). The higher the extraction rate, the more effective digits (enob). The disadvantage is that the group delay will also increase as the draw rate increases, so the designer must be compared between the signal resolution and the delay of the feedback chain. In general, the delay should be kept in a smaller range than the control cycle. For motor control, the typical draw rate is between 128 and 256, which can balance the signal-to-noise ratio and group delay.
In the data sheet specification, 256 is usually used as the extraction rate. For example, the ENOB of the ADUM7701 is 14 bits and the extraction rate is 256. When the enob value is so high, it is expected to be very accurate measurement results. In order to verify this, it is assumed that the phase current shown in Fig. 3 is measured at 20 MHz by σ-ΔADC, and the data flow is demodulated by SINC3 using 256 extraction. The result is shown in Figure 6A.
Figure 6. (a) the output of the SINC filter. (B) The actual phase current and the SINC filter extraction output waveform enlargement diagram.
The base wave component of the phase current is very obvious, but the measurement signal has a large noise as compared to the ideal sampling shown in Fig. 5A. Therefore, although the ADC and SINC filters itself provide a good ENOB number, the quality of the feedback signal is very poor. It can be seen from Fig. 6B, which is the waveform enlargement of the SINC filter output and the actual phase current. Note how the 10kHz switching component of the phase current occurs, and it is almost not attenuated by the SINC filter. Now, it is assumed that the primary motor control algorithm is performed in each PWM period and the latest SINC filter output is read at the beginning of the period. In fact, the output of the SINC filter will sample down to match the update rate of the control algorithm. The down sample and the resulting signal are shown in FIG. 6B as sample SINC output. Figure 7A shows the result of the entire fundamental cycle of filtering and sampling according to PWM rate.
Figure 7. (a) Sampling Output of the SINC Filter. (b) Measurement error.
Obviously, the phase current measurement is serious, so the control performance will be very poor. Thus, the torque ripple should be increased and the bandwidth of the current control loop is needed. From the ideal measurement value (Fig. 5A), the measurement value in Fig. 7A can be obtained (Fig. 7B). The error is approximately 7% of the original proportional signal, and is far from the expected 14enob.
This sigma-delta measurement and aliasing scene show the very common current measurement mode based on σ-Δ, and how it guides the designer to obtain "σ-ΔADC is not suitable for motor drivers" conclusions. However, this example does not show the poor performance of the ADC itself. Instead, since the phase current measurement is not set correctly, the performance of the remaining signal chain is poor.
The ADC samples on the input signal at a few mega (typically 10MHz to 20 Hz), and the SINC filter effectively removes modulation noise when the draw ratio is 256. At such a high sampling rate, there is a phase electrical fluid component in the filter output, which may become a problem (see Figure 1) in the downward sample level of the signal chain. If the ripple component is not sufficiently attenuated, and the motor control algorithm consumes current feedback with the PWM speed, the result will be aliasing due to the sample.
According to the standard sampling theory, in order to avoid aliasing, there must be no energy in half the sampling frequency. If the sigma-ΔADC output is sampled down to 10kHz, the noise at 5kHz or higher frequencies will be aligned into the measured value. As shown, there is still a large amount of 10 kHz switch noise in the signal after the SINC filter. One way to reduce 10kHz noise is to increase the extraction rate, but doing so will result in an unacceptable long group delay. We need to use a different way.
Improve measurement by synchronous
The main problem of the anti-aliasing method discussed in the previous section is shown in Figure 8. The output of the SINC filter is read at a time that is not related to the phase current switch component. When the output signal is read, the filter performs weighting average based on the impulse response input signal. This weighted average sometimes spans the low switch waveform, sometimes spanning the high point. Therefore, the signal used as feedback contains significant noise, and the frequency is from one half of the frequency of 0 Hz to the PWM.
Figure 8. Pulse response is independent of the switch waveform.
The sigma-ΔADC continuous sampling, the SINC filter output multiplies the measured value (usually 10 to 20) by each PWM cycle. Since each measurement spans three extraction cycles, the pulse response will overlap. For simplicity, only three measurement / impulse responses are shown in Figure 8.
The root of the problem is that the pulse response is not locked as the switching component of the current, and the switching component is locked to PWM. The solution is to select the extraction rate, so that each PWM cycle has a fixed integer extract period. For example, if the PWM frequency is 10kHz, the modulator clock is 20MHz, the extraction rate is 200, then each PWM period is exactly 10 extraction cycles. Each PWM cycle has a fixed sampling cycle, and the impulse response is always locked to PWM, and the measured value for feedback is captured in the PWM cycle. The phase current measurement of this synchronization scheme is shown in Figure 9A.
Figure 9. (a) Pulse response locks the sampling output of the SINC filter when the PWM is used. (b) Measurement error.
Obviously, the response synchronization and PWM synchronization will have a positive impact. The noise will be eliminated, and at first glance, the measurement results appear to be similar to the ideal measurements in Figure 5A. However, when the σ-Δ measure value is degraded with the ideal measurement value, the error signal shown in Fig. 9b is obtained. The error size is similar to the value shown in Figure 7B, but the spectrum changes. Now, the error is a first-order harmonic, which is equivalent to the gain error. The reason for this error mode is shown in Figure 10.
Figure 10. Pulse response is locked as a certain fixed point in the switch cycle.
Although the white noise error component is eliminated, the signal is still disturbed due to the measured value being affected by the switching component. In Figure 10, it is Note how the pulse response of the SINC filter will give the weighting average around the peak of the switch waveform. The size of the deviation is only limited by the size of the ripple current based on the phase of the pulse response relative to the PWM. As shown in FIG. 3, the magnitude of the ripple component changes in the fundamental wave period, the ripple is the highest, and the zero point is the lowest. Therefore, the measurement error is a first-order harmonic component.
In order to eliminate the first order harmonic measurement error, the impulse response must always be centered on the starting point or center of the PWM cycle, and the phase current is equal to the average value. Figure 11 shows a pulse response centered on the starting point of the switch cycle. Surrounding this point, the switch waveform is symmetrical, so by having the same number of measurement points in each side, the ripple component is zero around this point.
Figure 11. Pulse response is locked as a switching cycle, and an ideal measurement point.
When the impulse response is locked, the measurement results are shown in Fig. 12B as shown in Fig. 12A at the time of the average current. As an ideal sampling measurement, this signal does not have white noise and gain error.
Figure 12. (a) Pulse response locking adopts PWM, and the sampling output of the SINC filter is output when the average current is time. (b) Measurement error.
The results show that the quality of the σ-Δ measurement is not only dependent on the extraction rate. This view that is generally considered to "increase the extraction rate increase enob" is correct when it is unmisting. The update rate and phase ratio of the control filter relative to the input signal are more important than the extraction rate. For example, comparing FIG. 7 (based on 256) and Figure 12 (based on 200 based extract). Reducing the extraction rate can significantly improve the measurement results.
in conclusion
In summary, the conditions for achieving σ-Δ-optimized phase current measurement values are as follows:
The pulse response time of the three-order SINC filter is 3 extraction cycles, which means that the data requires three extraction cycles to pass the filter.
The pulse response of the filter must be centrally centered on average current.
The 1.5 sampling cycle of the pulse response must be before the average current, and the other 1.5 sampling cycles must be after the average current.
The SINC filter generates multiple outputs in the PWM cycle, but only one of the outputs. The rest of the output is ignored.
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