"First of all, I want to emphasize that I am not doing the back end, but the work is often encountered and colleagues to do the chip market and discuss PPA At this time, the back end will come up with such a table:
The figure is a back-end A53 of the results achieved, the node is TSMC16FFLL +, we interpret this to the next.
First of all, we need to know, as an ideal mobile phone chip company, you can choose not many factories, TSMC (TSMC), United Microelectronics (UMC), Samsung, GlobalFoundries (GF), SMIC (SMIC) barely count as one. Also, beginning this year, Intel Factory (ICF) will be open to the ARM processor. In fact someone has already begun to do, the physical library is not only used for third-party. The new process will usually choose TSMC, and then when you want to drop the cost will go to UMC. GF has been more alternative, the election can not be safe, and Samsung is not reason someone else so it did not care for him. As SMIC, hey, it needs to have a high ideal choice.
16nm meaning I do not specifically say, a lot of online explanation. And TSMC's 16nm node is divided into many small, FFLL +, FFC and so on. The highest frequency among them, leakage, there will be some cost differences for different chips, such as mobile phone chips like low leakage, low-cost server like high frequency, and so forth.
Then look at the first row of the table, Configuration. The easiest to understand, use a quad-core A53, a data cache 32KB, two 1MB, opened the ECC decryption and processing engine. These options will have a greater impact area, also has a smaller effect on the frequency and power consumption.
Next is Performancetarget, the target frequency. The frequency of the back-end engineer called Performance, when doing back-end implementation, must be in the frequency, power and area (PPA) was chosen as the main one main parameter optimization goal. This table is designed to do for high-performance A53, the higher the frequency, the greater the area and leakage, it is impossible to avoid. Later I report paste a small area of low power to do comparison.
Here is CurrentPerformance, which is now to achieve a frequency. Inside the TT / 0.9V / 85C What does it mean? We know that on a wafer (Wafer), not every point of the electron drift velocity is the same, and the voltage and temperature of different, their characteristics will be different, we classify them, there will be a PVT (Process, Voltage, Temperature), respectively corresponding to TT / 0.9V / 85C. The Process there are many Conner, similar to the normal distribution, TT is just one of them, according to the electron drift velocity can also have SS, S, TT, F, FF, and so on.
The results are usually back-end needs a Signoff conditions (which we usually SSG), in accordance with the conditions taped out, as a screening threshold, the chip will fail under, run less than the desired frequency. Therefore, the condition set lower, the yield (Yield) will be higher. But conditions are not set too low, or the back-end is difficult to do, or simply equation has no solution, no run results. There is a word called constitution on X86, it is this PVT.
This column has four frequencies, up and down easily distinguish between the two groups, that is, different voltages. When determining the frequency, dynamic power is the square of the voltage, we all know this. The difference between the two sets of figures is around the Corner, respectively, TT and SSG.
The next line is OptimizationPVT. We all know that the back-end EDA tools is actually solving equations, optimization need to give him a goal, it will automatically find the optimal local solution. 0.9V and 1.0V and must be selected from a value, as the most commonly used frequency desserts, power and area (SweetSpot). Here is the election of 1.0V, SSG and its objectives and requirements closer to those unattainable Corner can be used as down sale.
The next line is the leakage Leakage, is the static power consumption. CPU does not stop at that and consequently will have the power to run, which contains four logical CPU and cache leakage. A53 but does not itself contain secondary cache, some other small logic, such as outside the SCU (SnoopingControlUnit) are a CPU core, which is called Non-CPU, included in the MP4. When we stand is to see it, you can turn off twenty-three cache by powergating, but generally speaking, is not fully closed or not closed.
Here is DynamicPower, dynamic power. Basically I've seen in the measurement of dynamic power CPU time, we are running Dhrystone. Dhrystone is a very old run sub-program, basically doing string copy, very easily optimized software, compilers and hardware, as the performance index is basically only looked at MCU.
But it has the advantage that the program is small, a small amount of data, it can only run in the primary cache (if any), and the secondary cache and after all it is only the leakage circuit. Although access to two or even three cache DDR will cost more than a cache access of energy, but their delay is also large, and the CPU pipeline is likely to come to a halt. The consequence is that the greatest degree of consumption Dhrystone CPU core logic of power, to be higher than the program to access more than two cache. So often take Dhrystone as CPU maximum power consumption targets. In fact, you can write more power than the Dhrystone program, called MaxPowerVector, doing power estimation of SoC will spend time.
Dynamic power and voltage strong correlation. Formula which itself is a power of 2, then the voltage and frequency changes are also related, is the relationship between the three parties at the time of the voltage across. Although it is only 1.0V 0.72V higher than 39%, the dynamic power consumption may be a final 3 times. And when the high-frequency, dynamic power accounted for the majority, so the voltage should not be overlooked.
In addition, dynamic power consumption and temperature-dependent, time is running SoC impossible to maintain the temperature at 0 degrees, so the power will usually take 85 degrees or higher is calculated, this is not to say.
The next line is Area, area. Area of the chip company's foothold in this, and gross margin is directly related. Therefore, in the case in line with the performance, the smaller the better, even sacrificing power consumption, high voltage at the push, so with OD (OverDrive). There is data on the current 28nm, almost every square millimeter of the cost is 10 cents, an ultra-low-end mobile phone chips how have 30mm (200 dollars that mobile phone use, you may have never seen, or smart machine), is the cost of chip area knife 3, which also is not beta, storage and transport.
It has to be low-end 40mm (300 block cell phone). The most common of 600-700 dollars a mobile phone, which is one-sixth the cost of mobile phone chips. Of course, in turn, was also not short of money, such as Apple, said to the A10 done on 16nm 125mm, converted into A53MP4 here, just look at the area without regard to power, is enough to put 120 A53, extremely extravagant, this but running 2.8G of A53, if it is 1.5G, and 150 are likely to do so.
Apple such a large area that in the end is what to do? First, like GPU, Video, Display, baseband, the ISP modules, can easily take area are changing properties, it can be processed concurrently. Furthermore, the power consumption may take an area change, a simple way is down, increasing the number of processing units. Such leakage have increased, but the voltage drop, dynamic power consumption can be reduced a lot. One exception is a single-core CPU performance, why Apple can do Kirin960 of 1.8 times, the heat can accept? And physical libraries, back-end, front-end software have a relationship.
First, A10 6 is emitted, contemporary A73 only 2 emission. Of course, due to the data and instructions related constraints, performance is not three times the lift, and 6 are non-linear effects increase emission area and power consumption. As a comparison, I have seen models of ARM CPU 6 emission, under the same process, monocytes per Hertz performance A73 1.8 times the dynamic power estimation than 2-fold, also an area nearly twice. Of course, its microstructure and there is a big difference between A73. The single-core chip running at 16nm, 2.5Ghz, almost single-core power consumption is 1W. The mobile phone chip power consumption can not be maintained down at 2.5W, so Apple is doing the A10 2.3Ghz or feasible.
In order to control power consumption, making RTL when you need to insert additional transistors, do ClockGating, but this is graded on RTL-level, module level, system level, the clock signal there (I saw the clock usually accounts for the entire SoC logic third circuit power consumption). Such set out down a large area of at least 1/3. Then there PowerGating, also graded. The simplest is to a cache of each switch module has a switch. Depending complex instructions, which can be calculated in a short time without Cachebank, to shut it straightforward. PowerGating need delay will be greater than ClockGating, sometimes if the operation is very frequent, PowerGating but worth the candle, which requires careful consideration. Moreover, the more complex the design, the more difficult to write validation, there needs to be a balance. In addition to clock domain, power domains, as well as voltage domain, the voltage can be adjusted according to different frequencies. Of course, the multi-domain, routing more difficult, the larger the area.
Beyond that, you can define different powerstate, so that the top software also involved through to form a power management and scheduling.
Then returned to Apple A10, it uses 6MB of cache. The cell phones are also considered in great shock. Usually high-end A73 plus 2MB, A53 plus 1MB, has been on a very large, low-end add up to no more than 1MB. I get SPECINT2K done some experiments in A53, 128KB secondary cache from 1MB increase will only increase less than 15% of the performance, and that performance to 6MB / area gains more is not linear, it is naked area change performance. And Apple is not preached SPECINT, but GeekBench4.0, I suspect that is not the run points more sensitive to cache size, the time you can do some experiments.
Incidentally, security Bunny 5.0 and the cache size is not half dime, which makes the majority of high-end mobile phone chip company cause. 6.0 seems to change, and I have not carefully studied. As for the use of leakage caused by a large area of the cache, it does have a solution, and that is partially closed cache, how much open with, is a fine living, with the required hardware and software at the same time.
Factors affecting the area is not finished, just above the front-end, back-end considerations as well as a bunch of it.
The first is the form the next row, MetalStack. When the chip is manufactured by etching the layers, and etching the layers of coding when required, so that a key part of the visible light, referred to as Mask. 11m expressed herein on the layer 11. Transistor itself is at the bottom, and traces would have to walk from the top, the more likely the more layers, the wiring board made sure the students understand at a glance. This is fair to say that the extra layers, but the plant operator with your money is in accordance to the number of layers, the more the more expensive. Not only trace layers less difficult, the overall area of utilization is also low, as do 80% utilization A53,11 layer will be good enough. Therefore, the chip area than the sum of each small module is the overall area, have to consider the layout (PR, Placing & Routing), consider the area utilization.
Look at the table two rows, LogicArchitecture and Memory. This can be easily understood that the two logic modules and memory, digital circuits classification. This memory is a static memory, not on the outside of the DDR chip. What does it mean uLVT, UltraLowVoltageThreshold, it refers to the standard logic cell (StandardCell) with a low voltage threshold. Low voltage power for the dynamic course is good, but the standard cell leakage is also high, and the frequency is logarithmic, that is, the drain of each 10-fold increase, the maximum frequency was increased log10%. Critical path backend logic circuit may be provided to a constraint EDA tools, such as no more than 1% of the required frequency using punch uLVT, the rest are used LVT, SVT or the HVT (voltage is sequentially increased, reduced leakage), to reduce small overall leakage.
For dynamic power, the rear end can also customize the length of the source and drain of a transistor, the greater the narrower the current, the higher the leakage, the corresponding maximum frequency is higher can be washed. So sometimes we can see uLVTC16, parameters LVTC24 like, C here refers ChannelLength.
Next is the Memory, but also for MemoryInstance, it was also known as FCI (FastCacheInstance). Access Memory There are three important parameters, read, write and setup. These three parameters may be the same amount of time, it may not be the same. For a cache is used is substantially the same time, and is one clock cycle, and which of them can not flow. A73 from the beginning, I saw the back end of the critical path are stuck in the cache access. In other words, this path can do fast, CPU will be able to go fast frequency, and cache size also determines the size of the index, the greater the slower, lower frequency, high-end ARM CPU cache did not exceed 64KB, and it is closely related to the back-end. Of course, increasing the income level cache itself will bring the non-linear decrease. Twenty-three after the cache, a multi-cycle access, multi-bank may be accessed alternately, thus the size can be placed several hundred KB / several MB.
Collectively referred to as logic and memory PhysicalLibrary, physical library, which is based on the physical development process each packet to a node of the plant (PDK) design, while the bottom is a Library Fabless chip company can do. Be able to customize their mature physical library, the company is one of the leading back-end mark.
The last line, Margin. This refers to the factory in the production process, will certainly have a bias, and this line defines the scope of the deviation of the index. As shown below:
Blue represents the distribution we just said some of the Corner, the production of red deviation Variation. We have to do some test chips to correct these deviations. SB-OCV represents a stage-basedon-chipvariation, and several other variations are added together, a total of + -7%, that is to say there is not the result of the determination when the rear end of the design of 7% of the chip.
And there are a number of setupUC like, a signal indicating the setup time, hold time of uncertainty (UnCertainty), as well as the jitter range of the PLL.
At this point, a report is interpreted, let's take a look at the corresponding low-power version of the version:
Here the frequency drops to about 1.5g, and each GHz has a dynamic power consumption of less than 10%, but static reduces to 12.88MW, only 25%. We can see that LVT is used here, there is no ULVT, which is one of the reasons why static can do. Since the area is not optimized, it is basically unchanged, this is also understandable because the Channel width is different, and the logical area cannot be smaller.
Original link: https://www.eeboard.com/news/soc-6/6/
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