I believe that no one doesn't know Huawei, then Huawei as the world's largest communication equipment, how do you know how Hua's base station is designed? Which chips are it? What is the PCB circuit design structure? With a pile of problems, we dismantled Huawei RRU3908, an outdoor wireless base station, and its radio front output power was 20/40 watts.
The duplexer of the base station seems to be an iris coupled cavity filter, coupled to some cavities. The coupling of inputs and outputs is T, which is a connection portion on the resonator, not a coupled loop. The frequency is adjusted by a capacitor cap. The filter is a wide signal band.
If you can see the response speed of the filter, it is better.
Central processing unit
Network communication is handled by Freescale MPC8321 PowerQuicc2 CPU, and the CPU runs in 200 MHz and has 2X 256 MB HYNIX DDR2 RAM. It uses a PMC Quadphy 10GB controller for two optical input / output.
ADC and DAC single bitstream decoding and encoding are processed by 3 Altera Cyclone III FPGA and custom Huawei SD6151RBI controller.
The Huawei base station uses Texas Instrument TMS320 Series DSP processors to process single bitstreams. TMS320C6410 is a fixed point DSP that only calculates an integer, TMS320CT16482 1 GHz DSP CPU calculates a floating point number.
Signal receiving part
The input signal comes from two loss lines, first by SkyWorks Sky73021-11 1.7 - 2.2 GHz down-frequency mixer, resulting in a frequency of 2.2 GHz to 550 MHz.
The local oscillator of the down-frequency mixer is analog device ADF4110B.
A SIPAT saw filter is used for isolation.
Depending on the source or type of signal or type, it is assumed that the analog device AD8376 variable gain amplifier is used prior to the signal line is divided into a 3G ADC line or 4G ADC line.
3G line analog to digital conversion is processed by analog device AD6655-10, which is a 14-bit 150 MSPS chip that specifically for 3G base stations.
There are some components in the 4G line, such as the two-way HSWA + 1110 field RF switch, for the dual channel MAX2039E / DOWOCONVERSION mixer and through an additional recovery period HSWA + 1110 field RF switch is 200 AD9230 - 11 - 200 ADC chip number of 200 .
All timings are processed by analog devices AD9516-3, which is a 14 output clock generator with built-in 2 GHz local oscillator.
Signal transfer section
Altera Cyclone III FPGA's single bit data stream is processed by two analog devices TXDAC AD9788, and TXDAC AD9788 specifies for 16-bit 800 MSPS.
In order to raise the frequency of the signal to the broadcast carrier frequency, two simulation device ADL5375-05 upper variable modulators are used. They range from 400 MHz to 6GHz.
The signal is then transmitted through a 5-stage ceramic resonator band pass filter.
The signal phase can be switched from the arrangement of transistors and EMC technology and HPJ2F hybrid coupler in Florida RF laboratory.
The pre-amplifier sends to the pre-amplifier before the power amplifier for the Freescale MMG3004NT1 high linear amplifier, can enlarge 17 dB within 400 MHz ~ 2.2 GHz.
In order to control the signal strength, the MCL 31R5 digital step inaine is located before the output connector. This is a 31.5 dB attenuator that can be connected from a 6-bit serial control interface at 0.5 dB steps.
Power amplifier
The power amplifier uses two phases. The first stage is the English PTMA180402FL 40 watt wavelength flux LDMOS. By the Xinger II XC1900A-03S hybrid coupler, two 90 degrees non-phase signal feed to the output stage transistor NXP BLF6G20LS-140 140 watts RF LDMOS.
The output is recombined in the Xinger II XC1900A-03S hybrid coupler and then enters the duplex by the circulator.
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