IDT launches wireless base station RF card low noise timing chipset

Idt® Company (INTEGRATED DEVICE, INC .; NASDAQ: IDTI) announced today to optimize the low noise timing chipset to meet the wireless base station transceiver (BTS) RF card application. This new chipset product has complemented the wide communication signal chain product line of IDT, providing engineers to help them solve phase noise-related challenges and establish a first-class wireless system. The IDT 8V19N4XX chipset includes JESD204B compatible flexible RF Phase Ring (RF PLL) and clock-enactor that meets high frequencies and low phase noise in 2G, 3G and 4G LTE wireless infrastructure. This low phase noise characteristic enables system analog to digital and digital-to-analog converters (ADCS / DACS) to achieve high precision and low distortion. This also increases signal transmission integrity and signal reception sensitivity, and increases data throughput by lower bit error rate (BER). In addition, the reduction in noise in the RF signal path helps the base station developer reduces the requirements of the system filter, thereby reducing cost and complexity. CHristian KermarRec, vice president of IDT, said: "We realize that noise will have an adverse effect on RF signal chain, and develop this timing chipset, providing new tools for system engineers to solve this problem. The .idt new chipset also has multiple key features, including JESD-compatible clock features, and integrated clock shake figures that can be integrated with customer-specific architectures. This new timing device is not only conducted on our industry's leading timing product line not only Supplements, and also expanded other products, including performance-oriented data converters, data compression, Rapidio® and RF signal chain products for wireless infrastructure applications. " The IDT 8V19N4XX chipset can generate synchronization and highly configurable clocks and SYSREF signals required for JESD204B applications. This allows customers to adopt a standard timing chip with high flexibility and cost-effective ratio, rather than multiple locking rings, synthesizers, and buffers. In addition, the device has an integrated clock jitter attenuation characteristic, simplifies system design, and reduces system cost by supporting low cost, low frequency external VCXO.

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