Microchip subsidiary microSemi device design engineer Amaury Gendron-Hansen
Microchip subsidiary MicroSemi SiC Technology Development Director Avinash Kashyap
Microchip subsidiary MicroSemi Device / Development Engineering Director DUMITRU SDRULLA
The latest trends in the semiconductor market is widely used in silicon carbide (SiC) devices, including Schottky Barrier Diode (SBD) and power MOSFETs for industrial and automotive applications. At the same time, due to the limited field data available, the long-term reliability of these devices becomes a hot problem that needs to be solved. Some SiC vendors have begun to authenticate SiC devices based on strict industrial and automotive (AEC-Q101) standards, while others not only exceed these certification standards, but also provide data for harsh environment tolerance testing. In order to maintain a high penetration rate in task and security key applications, such authentication and test strategies should be combined with specific design rules to achieve high avalanche tolerance. This is important.
Rapid market
The market share of SiC devices is expected to accelerate growth in the next few years, mainly driving factors are electrification in the transportation industry. The SIC dies will become the basic components in the modules of the applications such as the vehicle charger and power transmission traction system. Since the critical electric field of the avalanche breakdown is higher, the shape of the high pressure SiC device is much smaller than the similar silicon, and can operate at a higher switching frequency. The thermal performance of SiC is also very good, which not only has good heat dissipation performance, but also work at high temperatures. In fact, the highest operating temperature is usually up to 175 ° C, rarely more than 200 ° C, mainly limited to assembly process (welding metal and package material). The SiC device is essentially more efficient than the silicon devices, switching to the SiC die can greatly reduce the number of individual dies in the module.
As the SiC device turns from the niche market to the mainstream market, the main challenges associated with large-scale production climbing effects are gradually being overcome. To easily implement this transformation, the manufacturer is building a SiC production line that can share the shared tools of existing silicon production lines. This arrangement can effectively reduce the cost of the SiC dies, as this can be shared with the Si production line. As wafer suppliers have greatly improved capacity, the restrictions in the wafer supply have recently been no longer a problem. Due to the continuous improvement of 4H-SiC substrates and epitaxial growth, it is now possible to provide a high quality 6-inch wafer having a very low crystal defect density. According to the electrical parameter test, the higher the wafer mass, the higher the yield of the SiC device.
But be sure to remember that because these devices are only available for a few years, their live reliability data is very limited. In addition, since the SIC device itself faces a series of challenges, it is much more difficult to certify the cardiac device. In the SIC device, the electric field under reverse bias conditions is nearly one quantity. This high electric field is easy to damage the gate oxide layer if appropriate design rules are not used. The trap density near the SiC gate oxide layer is also much higher. As a result, instability may occur during aging test due to traps. We have always focused on improving long-term reliability, and the results achieved are also gratifying. The recent report display device has been certified by strict industrial and automotive (AEC-Q101) standards.
In addition, SiC suppliers have begun to take the next step to provide data for harsh environment tolerance testing.
Harcyological tolerance test
As an example, Microchip performs harsh environment tolerance testing on SiC SBD and MOSFETs applicable to 700V, 1200V and 1700V voltage nodes. Test indicates that high-level non-clamp sensing switch (UIS) tolerance is critical to ensuring long-term reliability of devices. At the same time, it also indicates that high transient current flows through the reverse bias device during the UIS test and drives it into the avalanche. Under the common action of high current and high voltage, a large amount of heat is generated and the temperature rises sharply. Durable power MOSFET's local maximum temperature can reach 500 ° C, which is much higher than the typical temperature rated value.
UIS's tolerance is closely related to the front end of the production line and the rear end of the rear end. Even in extensive microcrystallization defects or defects related to process may constitute weak links, the devices have expired during the UIS test. This explains why a single pulse and repetition UIS (RUIS) test should be included in the comprehensive analysis of product line tolerance.
Single pulse test is used as a screening test for identifying a lower UIS tolerance. In order to ensure the UIS rated value in the product data sheet, all devices should be tested before delivery. However, the device may experience multiple UIS events during the field investment. In order to analyze the characteristics of gradually wear, it is necessary to repeat the test. To deeply analyze characteristics, apply a large amount of pulse to the device, and the common practice is 100,000 shocks.
During the UIS pulse, the current in the measurement device is continuously decreased, while the voltage is substantially constant, but will slightly change due to thermal effect (Fig. 1). The energy of the UIS pulse is defined by the maximum current and load of the pulse. During the test, the energy is adjusted by changing the inductance value. The maximum current is kept constant; it is equal to the forward current rated value of the SBD, and is also equal to two-thirds of the drain current rated value of MOSFET.
Figure 1: Ruis test settings during the UIS pulse and the waveform of current and voltage
Ruis test has a specific constraint condition, main purpose is to prevent a pulse from accumulating with the temperature of the next pulse. Before applying a new pulse, be sure to ensure the temperature of the device is close to the ambient temperature. In the test setting shown in FIG. 1, the temperature of the device is used to monitor the temperature of the device, and the pulse repetition frequency is adjusted to obtain a constant reading. To help the cooling device, it should be mounted to the position of the fan on the radiator.
Device design for high avalanche tolerance
In addition to adopting an appropriate test process, first-class UIS tolerance requires the following set of design rules:
The high-pressure end is designed with a sufficiently high intrinsic breakdown voltage to ensure that the effective area first enters the avalanches. In this case, the energy will be dispersed throughout the effective area, rather than in the end of a narrow, and the latter case will result in premature failure.
The electric field shield in the JFET area of the MOSFET is critical to the protection gate oxide layer. The design and implantation scheme for defining the P-type doped wells for the JFET region should be carried out to provide sufficient shield without seriously affecting the on state resistance.
The path is provided by dissipation of a passivation material having high thermal conductivity to heat through the top of the die.
Schottky diodes and power MOSFETs using these rules are good in harsh environment tolerance testing. The test of the SBD continues until a single pulse and repetition of UIS fail, and also monitors multiple DC parameters. The results of this test show that the forward voltage and reverse leakage current of the device are very stable, and the reverse breakdown voltage increases slightly, which can be attributed to the free carrier capture near the SiC. The pulse energy before failure is as shown in Figure 2. UIS tolerance is increased with an increase in rated voltage. In view of the fact that most of the heat is generated in the epitaxial region, this trend is not difficult to explain. As the extension thickness increases due to the increase of rated voltages, the heat generated per unit volume will decrease, which in turn reduces the temperature in the device. Due to repeated testing, UIS's tolerance is systematic, but the degree is small. Compared with single pulse UIS, the difference is less than 10%. Multiple UIS pulses do not have a strong accumulation effect, and the SBD is expected to maintain high tolerance during on-site investment.
Figure 2: 700V, 1200V, and 1700V SiC SBD failure each of each activity area
MOSFET harsh environment tolerance characteristics should focus on long-term reliability of the gate oxide layer, which does not require pressing the device to fail. Alternatively, a repetitive test consisting of 100,000 energy relatively low pulses can be used. For example, Microsemi 1200V / 40 MΩ MOSFET is designed using an avalanche tolerance, and is tested by 100 mJ pulses whose single pulse UIS rated value is 2.0J. Most DC parameters are not affected; however, because the test is pressed against the gate oxide layer, the moderate increase in the gate leakage is observed. In order to determine if the long-term reliability is damaged, we applied a dielectric breakdown that varies over time. Figure 3 reports the failure time when a 50 μA DC current is applied to the gate of various devices, including the MicroSemi SiC devices developed using the company's avalanche tolerance and other three leading supplies provided by other three leading suppliers.
Figure 3: TDDB failure time provided by the four suppliers provided by the 1200V MOSFET
Adhere to SIC
When using SIC devices in the industry and the automotive market, you need to meet stringent long-term reliability requirements. The best strategy to meet these requirements is to enable the product through the automotive AEC-Q101 standard certification, and conduct characteristic analysis of extremely environmentally withdrawal tests. It is also important to achieve high avalanche tolerance by applying design rules. When these measures are used together, it will not only help to ensure that the SiC device continues to advance on the path of rapidly, but also the long-term reliability required for these applications. Read more
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