Industry leading video codec library adds support for MSA

Currently, the digital entertainment world is experiencing a decree change. With the increasing popularity of video stream services, many companies have opened a new business model in this rapidly growing market. It is worthy of that the industry standard organization has been working hard to drive the industry to transition to high resolution video streams. Multiple teams have been working to find the most effective way to transfer video to mobile and embedded devices, including ITU-T (H.264 and H.265) and WEBM projects (VP8 and VP9). For the current codec, its main purpose is to maintain the same (or higher) quality than the previous version (or higher) while achieving a significant reduction in bit rate. For many mobile and embedded applications, this means that multimedia codecs must be optimized to address continuously enhanced computational complexity and meet equipment low power and low cost requirements. Video codec most typical architecture Until today, the optimization process still implicitly understands the depth understanding of the underlying hardware and a particular micro-architecture handwritten code. However, this method is sometimes the nightmare of developers because they must maintain the code tree for different architectures and platforms. VP9 vertical motion compensation filter To solve this problem, imagination releases the MIPS SIMD architecture (MSA). This is a set of standardized instructions aimed to meet the needs of the majority of computational intensive applications. Recently, on the white paper published in our website, we introduced how developers use MSA technology to optimize video codecs in a flexible, scalable and seamless cross multiple platforms. These optimizations can be officially used for FFMPEG V2.8.1 (HEV, VP9, VP8, AVC, MPEG-4 / H.263, MPEG-2) AVC encoder under X264. We developed an optimized and cross-platform built-in data type and internal function library to accelerate the operation of the video codec on the MIPS P-class and the I-Level Card CPU. This new method includes commonly used mathematics or arithmetic vectors (plus, minus, multiplier, transfer, etc.), and completely replacing the hand assembly code, allowing the platform that integrates the MSA-Capable MIPS military CPU Use it again. It also helps enhance maintainability and a lot of development time, making future MSA architectural code easier to transplant. The code is handled in readable structural sequence to make the register usage and instruction scheduling more intelligently. Finally, it has been added, and its performance is very competitive. For example, in the case where the VP9 codec is perpendicularly filtered, our total number of instructions is reduced to 10 times. For more information on MSA and optimize video codec, please download the white paper on the official website. If you want to know the prototype software of the MSA-Capable military CPU, we integrate related features in the free Codescape SDK released by the PRPL Foundation Latest Publish QEMU emulator and Imagination. Advanced users can contact us to get a professional version of Codescape SDK.