In the recent architectural day event, Intel rarely announced the CPU, GPU architecture roadmap, and a series of related technologies, strategic planning, and a series of related CPU architectures, and the new CPU architecture is very concerned. Highlights. This article collects some information to do some simple interpretation for everyone.
In the past three years 2019-2021, Intel will launch a generation of high-performance Core architecture (of course, in 2019-2023, will launch three generations of low-power "architecture, focus Of course, the former.
The high-performance new architecture in 2019 is "Sunny Cove", and the CPU is upgraded, and the 11th generation core graphics card is integrated. It uses 10nm process manufacturing, the desktop processor "Ice Lake", this will also be Intel The first 10nm product of the first scale.
2020 is "Willow Cove", almost a 10nm process, but should be optimized as 14nm +, 14nm ++, 2021 is "Golden Cove", I don't know if I can use 7 nm.
For Willow Cove, Golden Cove, Intel just briefly mentioned some of the main features, and INNY Cove in front of you, Intel announced a lot of architectural techniques.
First of all, this should be the first time in Intel's history before the new product release, the road map and technical details are raised, and the first large-scale application 10nm new process will be used, so 10nm sunny Cove Announced, attracting the extensive attention of the industry and even ordinary users.
Whenever a generation of new CPU architecture is published, it is very excited when it is very excited. It is also worth applauding, which is a series of fierce materials in advance.
However, it is slightly unfortunately, the information given by Intel is not complete, mainly introduces the back-end design details of the Sunny Cove architecture, and does not involve the front end portion of the instruction dispatch, the command queue.
The architecture of Sunny Cove can be divided into two parts. First, the general purpose performance is improved, and the second is the specific purpose performance improvement.
The improvement of generic purposes is enhanced through architectures, improves the performance and energy efficiency of a large number of applications, almost everyone can experience in daily use, which is essentially the change in the throughput of the original IPC (number per clock cycle instruction), or Running frequency improvement.
No matter what the process nodes, as long as these two points have an improvement, the overall performance will rise, at least in terms of the calculation, there will be directly reflected.
Frequency is often dependent on process and optimization, IPC can come from wider, deeper, smarter kernel, or professional point that is more instructions per clock cycle, more parallel per clock cycle, better transfer through the front end data.
The improvement of specific purposes is for specific use scenarios, algorithms to architectural extensions, including new instruction sets, new software compilers / libraries, etc.
This change can only experience a special occasion, such as Intel Promotion Sunny Cove Architecture, allows 7-zip software compressed decompression performance to increase up to 75% by newly joined instruction sets, is a typical example, only this Software or other software optimized for the corresponding instructions can usage significantly.
Special purpose performance improvement although the application range is limited, as long as the space is given, the effect is extremely significant, and the amplitude is far more common performance.
Sunny Cove also has a large number of improvements in this regard, involving artificial intelligence / machine learning, adding reconciliation, compression / decompression, communication / network, universal SIMD (single-instruction multi-data stream) / vector processing, special SIMD / vector processing, more Threads and multi-agent processing, etc.
If you have these applications, the changes brought by Sunny Cove are very considerable.
The upper side is some of the large applications, and there is a more exact application scenario in each area. The introduction of the new directive can greatly accelerate the execution of a specific computing task. As the AVX-512 instruction unit is added, Sunny Cove is an increase in IFMA (symbol melter algorithm), or is also used to add confidence.
At the same time, there is a vector AES encryption (support more AES instruction parallel), vector carryless multiply, Galois Field, SHA / SHA-NI security algorithm, etc., many of them are cryptographic Some basic elements.
In terms of caching, the Sunny Cove backend has a 48KB-level data cache, an increase of 50% than the current 32KB. In general, the square root of the cache's non-hit rate and capacity increases, that is, the error rate of the first-order data cache hits of Sunny Cove will be reduced by 22%.
Sunny Cove's second-level cache is also greater, but the specific capacity is not disclosed. Current Core is 256kb 2 cache per core, and is 1MB to strong.
In addition, micro-operation (UOP) caching is more than the current 2048-Entry design, but the specific number is not open.
The second-stage TLB also increases to the unknown, which helps the machine history address conversion. Normally, it is necessary to keep and store more polling, which means Intel has found that in some applications, the recent machine address has been recovered.
This picture shows more variations, including execution ports from 8 to 10, allows the scheduler to release more instructions at a time, where port 4, port 9 connected to cyclic data storage, double, AGU (address generating unit ) The storage capacity is doubled, and a larger level instruction cache has played a role in it.
There is a bottleneck in the previous Skylake architecture. When all three AGUs try to store, the bandwidth will be significantly insufficient, and one can only be performed per clock cycle.
The load performance is unchanged, while the width scheduling is increased from 4 to 5, which means that the distribution of the buffer can be hit by 5 instructions per clock cycle, but the actual effect is still to be observed.
Sunny Cove, the execution port of the Skylake architecture has undergone fundamental changes.
It can be seen that Intel is equipped with more LEA (effective address load) units to perform memory addressing calculations, which may be mitigated by security updates, or With a constant offset, high performance array code is helpful.
The MUL (Multiplication) unit transferred from Skylake's port 5 to port 1, which may be due to the purpose of balanced design, and an IDIV integer division unit is also added.
This change is not large, and 10 nm Cannon Lake also has a 64-bit IDIV that can reduce the 64-digit certificate from 97 clock cycles (mixed instructions) to 18, and Sunny Cove may also be similar to.
In terms of int integer operation, the multiplication unit of Skylake port 5 turns into a Mulhi unit, but the specific role in the new architecture is not clear.
In terms of FP floating point operations, Sunny Cove adds rearranged resources because Intel receives customer feedback, hoping to eliminate bottlenecks in the code.
Intel does not specifically describe the function of the core floating point part of the FMA (melting operation) unit, but we know that there is an AVX-512 instruction unit in the core, so at least one FMA unit will interact with it.
The Cannon Lake architecture has only one 512-bit FMA unit, which is likely to continue here, and there may be two in power.
In order to make a more clear comparison of Skylake, the rear end of Skylake, the foreign media Anandtech also made a comparison form:
Other kernels in Intel also have: branch predictor improvement, effective load delay (benefit from TLB / L1D), but Intel also admits that these improvements will not allow everyone to benefit, need new algorithms Use in a particular code.
In addition, Sunny Cove also supports greater memory, and the main memory paging is a 5-layer design (before 4 floors), the supported linear addressing space reaches 57 bits, and physical addressing space is 52 bits.
This means that the top-powered server platform can match up to 4TB memory, and the Skylake-SP architecture can be extended to 1.5TB, and AMD is just 2TB.
In fact, SUNNY COVE is an architecture that makes a major change in X64 virtual memory addressing since AMD 2003 introduced X86-64 64-bit architecture.
For more than a decade, although virtual memory addressing supports 64 bits, only the first 48 is useful, the 16 bits behind are just a simple copy, which limits the virtual addressing space to 256TB.
These virtual memory are mapped to physical memory through a pilot page, making physical memory memory addressing, resulting in the maximum physical memory of the entire system that cannot exceed 256TB.
Now, Sunny Cove will extend effective virtual memory addressing to 57 bits. The physical addressing is up to 52 bits. The result is virtual memory, and physical memory can support to 128PB, 4PB, respectively.
According to the road map given before Intel, the new generation of ICE Lake-SP family will be listed in 2020, and the memory expansion capacity will be improved.
In the way, in terms of security, Sunny Cove supports multi-key full memory encryption, user mode instructions.
As for changes in the front end of the Sunny Cove, we look forward to Intel publishing more information.
Sunshine Bay is full of artistic conception: Although the sky in this figure is not very sunny, it is true that Cove is beautiful.
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Original address: https://www.eeboard.com/news/sunny-cove/
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