FPGA (Field-Programmable Gate Array), on-site programmable gate array, which is a product that further develops on programmable devices such as PAL, GAL, CPLD. It is a semi-customized circuit in the field of special integrated circuit (ASIC), which has solved the deficiencies of the custom circuit, but also overcomes the shortcomings of the original number of the number of door-to-digital rectangularities. The development of FPGA is very different relative to traditional PCs, the development of single chip microcomputer. The FPGA is mainly in parallel operations, which is implemented in hardware description language; there is a great difference in the order of PC or single-chip (whether a Von Nioman structure or Harvard structure), it has also caused the FPGA development. At present, there is a domestic FPGA foreign-developing manufacturer, and the development of basic circuits is as follows:
The buzzer circuit is shown in Figure 3.47. The FM signal is controlled by the I / O port of FPGA. When the fm is high, the BE of Q1 is turned on, then the CE is turned on, the 5V and GND of the buzzer form a loop, and sound is emitted. When the fm is low, the BE of Q1 is disconnected, then the CE is disconnected, the buzzer 5V and GND are disconnected, so there is no current flowing over the buzzer, the buzzer does not sound. In the latter experiment, we can use the PWM signal, that is, the atmospheric level control Q1 is turned on, and then the time of the buzzer is reached, the human ear is different. The sound of the frequency.
Figure 3.47 Buzzer drive circuit
The circuit of 8 LED indicators is shown in Figure 3.48, and their public end is powered by 3.3V, and the other end is connected to the I / O port of FPGA. If the output is high, the LED is extinguished; if the output is low, the LED lights up. The 8 LEDs of the 8 LEDs are multiplexed with the digital tube selection signal.
Figure 3.48 8 LED indicator circuit
The 3-bit dial switch circuit is shown in Figure 3.49.
Figure 3.49 DIP switch circuit
As shown in Figure 3.50, we can control the actual object, the default 3 DIP switches should be allocated to the left (i.e., 1, 2, 3 mark side), on the circuit diagram, the VCC3.3 pull-up side. That is to say, by default, three signals SW_MODE1, SW_MODE2, SW_MODE3 connecting the FPGA I / O port are high. If the DIP switch is allocated to the right (ie the tag on side), the collected input is low.
Figure 3.50 DIP Switch Real Photo
The digital tube circuit is shown in Figure 3.51. The four signals of seg_cs0, seg_cs1, seg_cs2, and seg_cs3 correspond to the selection signal displayed by the digital tube 4-bit displayed, and the low level is valid. If the four pieces of selection signal is 0, the 4-bit digital tube can illuminate the display. The LED0-7 is also multiplexed as a segment selection signal of the digital tube, controlling the lighting state of the corresponding segment LED of a digital tube, which is shared for 4-bit digital tubes. In actual control, we generally light up the number of digits that need to be displayed, as long as the time is controlled reasonable, the human eye is very easy to be "cheated", we can easily see 4 different numbers display On the digital tube.
Figure 3.51 Digital Tube Drive Circuit
The circuit of the A / D chip is shown in Figure 3.52. It is connected to FPGA through a single-way (from A / D chip to FPGA) data. FPGA reads the current analog voltage value via this set of SPI interfaces. In order to obtain a different analog voltage value, our board sets a 3.3V voltage resistor at the analog input of the A / D chip, and adjusts the variable resistor R24 when the jumper is connected to the 1-2 pin of P3. The resistance can change the current A / D sampled data. If the jumper cap is connected to the 2-3 pin of P3, the input analog voltage of the AD chip is from the current output of the D / A chip.
Figure 3.52 A / D chip drive circuit
The D / A conversion circuit is shown in Figure 3.53. This D / A chip is connected to the FPGA through the I2C interface, and the FPGA outputs data by this group of I2C interface, and the VOUT of the corresponding D / A chip outputs analog voltage value. If the jumper cap is connected to the 1-2 pin of P2, the different analog voltage value output drive D9 indicator presents different brightness.
Figure 3.53 D / a chip drive circuit
FPGA (field programmable logic devices) products have been extended from the original communications to a wide range of fields such as consumer electronics, automotive electronics, industrial control, test measurement. The change of the application also makes the evolution trend of the FPGA products in recent years. On the one hand, the FPGA supplier is committed to enhancing the performance of the product, reducing the cost of the product; on the other hand, more and more General IP (intellectual property) or customer custom IP is introduced into the FPGA to meet the requirements of customers' products. In addition, FPGA companies have vigorously reduce the power consumption of products and meet the industry's increasingly demanding low-power demand.
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Source: Wiku Electronic Market Network
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