Keywords: ICL103, speed circuit diagram
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Author: 贵 荣 荣
The speed circuit is shown in the drawings. Its circuit is composed of a Hall magnetic sensing circuit, a time base control circuit, and a count, decoding, display circuit, and the like.
Digital tubes (SM1, SM2, SM3) use LCL103. It is the core component of the speed circuit. The LCL103 is an LCD-CMOS combination device, a set of counts, registration, display decoding, driving, and LCD (liquid crystal) digital tubes, high integration, and direct display / second or rotation / division. The CR of the LCL103 is a reset terminal; the LE register locks the control terminal; RBI, RB0 is invalid zero-implicit control input, output; BL blanking control terminal; DIP decimal point blanking control terminal; COM is a liquid crystal back electrode; VSS negative power supply; OSCI, / OSCO, OSCO is oscillating input, output; CO is the carry output; CP and EN are positive and negative pulse contacts; VDD is a positive power supply (4V ~ 15V).
Its shape has a size of 16 mmx24mmx8mm (uncharged), and the LCD digital tube width is 10.8 mm. The drawings use a 3-digit digital tube cascade, you should pay attention to the following: (1) Clock pulse is received by the lowest position input (CP ↑ or / EN), carry output signal (CO) (/ en); (2) The liquid crystal display requires a 50Hz to 400 Hz, the oscillation signal (f = 1 / 2.2xr6xc4) of the duty cycle (f = 1 / 2.2.2xr6xc4), and only one oscillator is used when using the cascade, and then remove the clock signal from its COM. The remaining Digital Tube OSCI That is; (3) invalid zero midden method is to make the highest bit RBI = 0, its RBO, high RBI, and so on, the lowest bit RBO is open.
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The turntable in the figure is to be rotated (or the motion conveyor belt), and the sensor IC1 uses the SH13 Hall integrated circuit. When the cartrust of the magnet is mounted. IC1 perceive magnet signals and records, enlarged and IC3-1 (CD4093B) reverse phase, plus the foot of the non-door IC3-3. IC2 uses a single-time base circuit NE555, composed of R2, RP, VD1, C1, uncondensed multi-resonation, oscillating cycle T = 0.693 (R2 + 2RP) C1, the RP adjustment oscillation period (the oscillation frequency of the illustration element parameter It is in the range of 0.05 Hz ~ 7Hz). The square spng pulse of the IC23 foot output is divided into three roads after IC3-2 reverse phase: all the way to the LE end of the digital tube LCL103, so that it is registered: another road. Limited circuits such as R3, C3, R4, R5, VD2, VD3. As the CR end of the LCL 103 as a reset pulse. Clearing a reset; the third road plus 8 foots with non-door IC3-3, count the brake door, IC23 foot output low level, IC3-38 foot input high, gate is open, you can send people to the foot Hall detection signal counts, registration, decodes, and display. When IC23 foot outputs high, IC3-38 is low, and the count gate is turned off. However, the digital tube LCL103 still has a port number (LE side), and the count content is sent to the register. And display the number. When the second time base signal arrives, it is cleared. And count, registration, decodes, and display again. So repeated test.
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