With the rapid development of FPGA technology, the size of the chip is continuously improved, which has brought more powerful performance. FPGA has a strong advantage in response to the calculation of the control complexity and the amount of data, which has a low amount of complicated complications and large amount of data. However, in the implementation of complex algorithms, FPGAs are far without 32-bit thin instruction sets computer (RISC) processors flexible, so when they are designed with complex algorithms and control logic, RISC and FPGA are often needed to use. The difficulty of such circuit design is also increased accordingly. Altera's Cyclone V SOC integrates the RISC hard processor system and FPGA together to achieve functional complementarity, greatly reduces the complexity and volume of hardware circuits, and also reduces power consumption and improves system reliability. This is definitely a gospel for embedded developers, because this architecture means higher system performance, lower power consumption (relative to dual chip solution), smaller board area and lower System cost. However, just like a talented artist needs a tailor-made stage to make the audience amazed the impression, and then powerful chips also need to design excellent peripheral circuits and interfaces to play their strengths, and this is the development of British The latest LARK Board evaluation board is the ultimate goal of ALTERA CYCLONE V SOC, providing an arbitrary display stage.
Block diagram of Cyclone V So
The Lark Board Evaluation Board is customized based on the three core resources of the SOC (ie traditional FPGA universal IO and logic, traditional ARM universal IO, and high-speed differential transceivers), providing on-board USB Blaster II JTAG online debugging. TF card and EMMC start, HPS and FPGA each exclusive 1GB DDR3 memory, SDI HD input and output, VGA and HDMI high-definition display, medium-sized LCD touch screen interface, high bandwidth analog front end and ADC sample, 10/100 / 1000M Ethernet, USBX4 interface, digital camera interface, PCIEX1 / X4 interface, RTC, HPS, and FPGA part extension, etc. extension interfaces and hardware resources. Below is the Lark Board system block diagram, which clearly shows how the evaluation board minuses the various functions of Cyclone V.
Let's take a look at these interfaces and hardware resources on the Lark Board to see how it makes Cyclone V So play in this stage that specializes in its design.
Lark Board in kind
1. Onboard USB BLASTER II
JTAG and USB Blaster II are the basic debugging tools developed by FPGA. Embest as an Altera Strategic Partner, get Altera authorized to use online USB Blaster II on the Lark Board, improve the efficiency and reliability of FPGA debugging, save the user to buy external Blaster's trouble, and eliminate the user's negligence forgetting the power Hot swaps External Blaster causes the burnout of the board. In addition, the onboard USB Blaster II can support Quartus II and ARM DS-5 development environments.
2. Support TF card and EMMC boot
Lark Board comes with a TF Card socket and 4GB EMMC, and users can choose from EMMC or TF Card from EMMC or TF Card.
3. Onboard DDR3 Memory
The SOC on the Lark Board integrates a hard DDR controller in the FPGA and HPS section, which is external to two DDR3 particles (each 1GB). HPS and FPGA can be accessed by internal bridges, maximum access space is 1GB, up to 800MHz (1600MBps).
4.SDI HD input and output
By configuring the SOC's own SDI transceiver, as well as the LMH0303 cable driver and LMH0384 equalizer on the board, the Lark Board can use the SMB coaxial to connect with HD IP CAMERA or DVR to achieve security monitoring, medical imaging, Application of car safety and other aspects.
5.Vga and HDMI
Lark Board Integrates CH7033B HDTV / VGA / DVI Displays the encoding chip, with a flexible image scaling engine, a simple digital audio configuration interface. Display support 1080 HDMI output, VGA display maximum support resolution can reach 1920x1080. Audio supports SPDIF and dual channel I2S audio input, and the high-fidelity audio decoding engine has a sample rate of up to 192k / 2ch, supports PCB coding data and Dolby / DTS compressed digital audio.
6.lcd touch screen interface
The 50pin LCD touch screen interface on the Lark Board can support up to 24-bit color data, and integrate the touch screen control chip, simply implement the coordinate data to the conversion of the standard SPI protocol data.
7.LNA (low noise amplifier) and ADC sampling
Lark Board Integrates Dual Channel 3.3GHz RF / Mediation ADC ADC, 12-bit 105MSPS, enlargement, filtering, and sampling of radio, intermediate frequency analog signals. Users can use this as prototype, combined with powerful operations and image processing capabilities of HPS & FPGAs, such as sampling oscilloscopes, software radio base stations, simulation / digital TV reception, GPS / Radar / Sonner reception Processing system, etc.
8.11 / 100/1000 MBPS Ethernet
Lark Board integrates an AR8035 single network port 10/100 / 1000MBPS Ethernet controller, supports MAC-side RGMII interfaces; providing low-cost, low-power network solutions.
9.USB PHY and HUB
The Lark Board contains the USB3320 high-speed USB2.0 physical layer transceiver and USB2514 USB HUB, with a maximum of 4 USB interfaces to easily implement the Host / Slave / OTG feature included in the USB protocol, and high speed, full speed and low speed transmission mode.
10. Digital camera interface
The Lark Board contains a 30PIN digital camera interface that can be connected to the camera via an FPC (flexible circuit board). Supports up to 12 digits of digital image input data.
11.PCI-E X1 / X4 interface
The Lark Board contains the PCI-E X1 / X4 expansion slot, and can easily support the extension application cards of various PCI-E by configuring the hard core of the FPGA.
12.RTC clock
The Lark Board contains the DS3231 clock chip, and the battery base can be accessed by the battery base on the board to access the clock management after the system is powered down.
13.HPS (hard-working processor system) section IO pin extension
The HPS part of the HPS section that is not directly utilized or having multiple significance is drawn through the standard 40PIN socket, so that the user can customize the extension and function customization according to their own applications, users can easily use the HPS integrated QSPI, SPI, I2C, UART , GPIO controller.
14. FPGA section IO pin extension
The FPGA section of the FPGA portion that is not directly utilized on the board is taken out by another standard 40PIN socket, so that the user can easily customize the hard core and logical resources in the FPGA according to their own applications. The custom application of high bandwidth function, supported transport protocols include LVDS, RSDS, SLVS, Mini-LVDS, etc.
Altera Cyclone SoC integrates dual-core Cortex A9 MPCORE processors, adopting advanced 28nm FPGA technology, its performance is not strong. As mentioned in the beginning of the article, no matter how talented in the artist, there is a suitable stage to play, the Lark Board has provided a huge stage for this powerful SOC, which can be on this stage. Realize the low-power, low-cost, high-bandwidth, high reliability, flexible customization, and fast listing required for embedded design, meet the application requirements of industrial control, medical, automotive and monitoring, plus The rich experience and custom design services, embedded applications and system designers can naturally achieve halving effect during the development process.
Related reading:
Arrow released an Altera Soc Development Board Cyclone V Sockit
Altera announces the start of the Cyclone V SoC development kit
Altera starts only $ 49 development kits extended low-cost series
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