When performing a chip test of a decimal frequency synthesizer, the digital portion can be achieved by a conventional digital test method; and the phase noise of the radio frequency signal is output, and the stray noise requires the chip to work in a normal output. The decimal frequency synthesizer chip requires an external loop filter (LF), and the voltage controlled oscillator (VCO) can constitute a complete lock-phase loop circuit, which can be implemented in the premise of normal chip functionality. Phase noise, test under spurious noise.
In general, the voltage controlled oscillator uses ready-made devices that pay attention to performance indicators when selecting devices, only loop filters are required to be calculated and designed. The loop filter is mainly used as a low-pass filter throughout the circuit. It performs low-pass filtering of the pulse signal output from the chipper, filtering the high frequency component, and finally obtains a relatively smooth DC voltage signal to control the VCO. Work, thereby obtaining a stable frequency output. The performance of the loop filter will directly affect the performance of the decimal frequency synthesizer chip.
In this paper, the ADF 4153 decimal frequency synthesizer is used as an example, and the design method of the third-order loop filter is given, and the needs of the actual test of the chip can be satisfied.
1 design of an external loop filter
The loop filter is an important part of the charge pump locking loop circuit, which is connected between the charge pump and the voltage controlled oscillator. The basic frequency characteristic of the phase locked loop is determined by the loop filter. In fact, it is because of the presence of loop filters, the phase-locked loop can be selected within any central frequency and bandwidth. The type of loop filter is widely divided into two major classes of the active filter and passive filter, and the passive filter is similar to the active filter, which is the advantage of: the structure is simple, low noise, high stability. Degree and easy to implement.
The most common passive filter is a three-order filter as shown in Figure 1. In general, the bandwidth of the loop filter should be 1/10 of the PFD frequency (channel interval). Improve loop bandwidth reduces the lock time. However, the loop bandwidth has greatly increased the unstable in the conference, resulting in a state in which the phase locked loop cannot be locked.
Figure 1 third-order loop filter
The transfer function of the third-order passive filter is:
In order to obtain the value of C1, C12, C3, and R1, R2, first, it is first necessary to determine the bandwidth and phase margins required for the design, and many documents give a detailed finding step, which is not disclaimed. However, this calculation method is more cumbersome when practical applications, which is not conducive to engineering design.
The AdisimPLL frequency synthesizer design software issued by Adi Company can easily design loop filters according to user use requirements. It frees the application engineers from a complicated mathematical calculation. Applicants can enter several key parameters for setting the loop filter, and the AdisimPLL can automatically calculate the value of the desired filter element. These parameters include: Tsing phase frequency PFD, charge pump current ICP, loop bandwidth BW, phase margin, VCO control sensitivity KV, filter form (active or passive, order). However, when testing, how to reduce the noise introduced by an external circuit (such as a loop filter) as much as possible to test the true performance of the chip, which is a problem that needs to be solved when the chip is designed.
2 loop filter design parameters
In order to study the influence of the loop filter to the phase noise of the phase-locked loop output frequency, the peripheral loop filter required for the chip test is designed. We have made the following simulation configuration in the AdisimPLL software. Device Model: ADF 4153, FPFD = 25MHz (ideal Signal), INT = 69, FRAC = 101, MOD = 125, VCO uses Zcomm's V674ME34-LF, and under this configuration, RFOUT = 1.7452GHz is expected.
A) Set the loop filter bandwidth of 20 kHz, phase margin 50 °, the simulation of its phase noise is shown in Figure 2.
Figure 2 Phase noise simulation chart at 20 kHz of loop bandwidth
From Fig. 2, it is possible to know that when the loop filter bandwidth is 20 kHz, the phase noise caused by the VCO occupies dominates. The phase noise caused by the chip is submerged under total output noise. In other words, when the loop bandwidth is narrow (such as 20 kH), the phase noise test is performed for the phase-locked loop output signal, and the result cannot truly reflect the phase noise output from the chip.
B) Set the loop filter bandwidth of 100 kHz, phase margin 50 °, and the simulation of its phase noise is shown in FIG.
Figure 3 Phase noise simulation chart when the loop bandwidth is 100 kHz
As can be seen from Figure 3, when the loop filter bandwidth is 100 kHz, the contribution of the total phase noise is significantly lowered, and the phase noise caused by the chip occupies the dominant position, within 10 kHz, the total phase noise output curve is basically The phase noise caused by the chip is coincident. It can be seen that when the loop bandwidth is wider (eg, 100 kHz), the phase noise test is performed for the phase-locked loop output signal, and the result is substantially the phase noise output from the chip.
The main test frequency of the ADF 4154 studied in this paper is 1.7452GHz (FPFD = 25MHz, RSET = 5.1K), and the comprehensive consideration is combined according to the test requirements, and the loop bandwidth is 75 kHz, the phase margin 50 ° constraint conditions are set. When the peripheral circuit design of the ADF 4153, the VCO model and its nominal performance are required to be confirmed. Then, the design of the third-order loop filter is performed according to the Adisim-PLL software provided by ADI. From the software, specific values of C1 to C3, R2, R3 are obtained, and then adjusted according to the existing nominal capacitance resistance value, and the loop bandwidth and phase margin of the actual design are used. The actual data is shown in Table 1.
Thus, we determined the value of each capacitor, resistance in the loop filter, and designed a circuit schematic can be used for the ADF 4153 chip test, as shown in Figure 4. The output of VCO not only needs to be connected to the external spectrometer, but also needs to feed back the capacitor to the refina end of the ADF 4153, and the REFINA is also required to reserve SMA heads for RF input frequency range and sensitivity testing. A simple resistance network is used to complete the redistribution of the VCO output signal power.
Figure 4 Loop filter and RF circuit design
3 loop filter test verification
On the basis of simulation, we designed and processed the Test board of the ADF4153, and the resistance value consisting of a loop filter network according to the calculated capacitance. The Agilent8257D RF signal source is supplied with 250MHz as Frefin, set FPFD = 25MHz, N = 69, 4/5 by SPI port, ICP = 5mA, FRAC = 101, MOD = 125. Using the spectrometer measurement output signal, Normal locked at 1.7452GHz, as shown in Figure 5. Figure 6 is a phase noise test diagram of the frequency point, the measured phase noise is -106.34dBC / Hz. The loop band is about 85 kHz, and there is a certain gap between 77.3kHz with theoretical value. This is due to the deviation caused by the parasitic capacitance of the test board trace and the test socket, but still within a reasonable range in the simulation.
Figure 5 Output signal spectrum
Figure 6 Phase noise test diagram
Test the phase noise and pseuding of the chip in different working modes, and the test results are shown in Table 2, 3.
The data manual specifies the lowest phase noise mode 5 kHz frequency offset phase noise PN ≤ -95dBc / Hz, which is measured to be -106.04dBc / Hz, and the test results meet the requirements.
Data manual specifies a stray Sn ≤ -65dBC / Hz in the intermediate stray mode, which was measured to be -84.99 dBC / Hz, and the test results were met.
In summary, the filter is designed to achieve the expected design goal, meet the requirements of spurious and noise testing in different modes, and can be used for performance testing of the ADF 4153 chip.
4 Conclusion
This paper mainly based on chip test purposes, for discussion for loop filter design in peripheral circuits, a simple, easy engineering calculation method and process is given, and verify testing, test results are met Needle of chip test. This method has been applied to the design of the test circuit of a variety of decimal frequency synthesizers.
Be
Be
Source: Wiku Electronic Market Network
Our other product:
