Many Precision Analog Converters (ADCs) have a serial peripheral interface (SPI) or a serial interface for communicating with a controller including a microcontroller unit (MCU), DSP, and FPGA. The controller writes or reads the ADC internal register and read the conversion code. The SPI's printed circuit board (PCB) wiring is simple, and there is more popular clock rate than in parallel interfaces. Moreover, using standard SPIs easily connect ADCs to the controller.
Some new ADCs have SPI, but some ADCs have non-standard 3-wire or 4-wire SPI as slave because they want to achieve faster throughput. For example, the AD7616, the AD7606, and the AD7606B series have two or four SDO lines that provide faster throughput rates in serial mode. AD7768, AD7779 and AD7134 series have multiple SDO lines as SPI hosts. The user will often encounter difficulties when designing microcontroller SPI to configure ADC and reading code.
Be
figure 1. The AD7768 is used as a serial host with two data output pins (14001-193).
Standard MCU SPI connection with ADC
SPI is a synchronous, full duplex, master-slave interface. Data from host or slave are synchronized in the clock rising or falling edge. The host and slave can transmit data at the same time. Figure 2 shows a typical 4-wire MCU SPI interface connection.
Be
figure 2. Connection with ADC slave standard MCU SPI
To start SPI communication, the controller must send a clock signal and select the ADC by enabling signals (usually low-level effective signals). The SPI is a full-duplex interface, so the controller and the ADC can output data simultaneously through MOSI / DIN and MISO / DOUT lines, respectively. The controller SPI interface allows the user to flexibly select the rising edge or falling edge of the clock to sample and / or shift data. In order to carry out reliable communication between the host and the slave, the user must comply with the digital interface timing specification of the microcontroller and the ADC chip.
If the microcontroller SPI and the ADC serial interface have standard SPI timing mode, the user is designed to design the PCB wiring and the development of the drive firmware is not problematic. However, the serial interface port of some new ADCs is not typical SPI timing mode. The MCU or DSP does not seem to read data by the AD7768 serial port (a non-standard timing SPI port), as shown in Figure 4.
This article will introduce a method of manipulating a standard microcontroller SPI for an ADC interface with a non-standard SPI port.
This article gives four solutions that read the ADC code through the serial interface:
Solution 1: The MCU is used as the SPI slave, through a DOUT line with the ADC interface as a SPI host.
Solution 2: The MCU is used as the SPI slave, and the two DOUT lines are connected to the ADC interface as the SPI host.
Solution 3: MCU as a SPI slave, through DMA and an ADC interface as a SPI host.
Solution 4: The MCU is used as the SPI host and the SPI slave, and data is read through two DOUT lines.
Be
image 3. SPI data clock timing diagram example
Be
Figure 4. AD7768 FORMATX = 1 × timing diagram, only by DOUT0.
STM32F429 microcontroller SPI reads AD7768 code through a DOUT cable
As shown in FIG. 4, when FormatX = 11 or 10, channels 0 to passage 7 output data only by DOUT0. In standard operating mode, the AD7768 / AD7768-4 operates as a host, data flows into MCU, DSP, or FPGA. The AD7768 / AD7768-4 provides data, data clock (DCLK), and falling edge frame enable signal (DRDY).
The STM32Fxxx series microcontroller is widely used in many different applications. The MCU has multiple SPI ports that can be configured as a SPI host or slave using a typical SPI timing mode. The methods described below can also be applied to other microcontrollers having 8-bit, 16-bit or 32-bit frames.
The AD7768 / AD7768-4 is 8 channels and 4-channel synchronous sampling sigma-delta type ADC, each channel has a sigma-delta modulator and a digital filter, synchronous sampling of AC and DC signals. These devices have realized 108 dB dynamic ranges at the maximum input bandwidth of 110.8 kHz, with ± 2 ppm INL, ± 50? V Offset error and typical performance of ± 30 ppm gain errors. AD7768 / AD7768-4 users can trade between input bandwidth, output data rate, and power consumption, and select one of three power modes to optimize noise goals and power consumption. The flexibility of AD7768 / AD7768-4 makes it a reusable platform for low-power DC and high performance AC measuring modules. Unfortunately, the serial interface of the AD7768 is not a typical SPI timing mode, and the AD7768 acts as a serial interface host. In general, users must use FPGA / CPLD as their controller.
For example, use 32F429IDiscovery and AD7768 evaluation boards. The connection to the SPI line is shown in Figure 5. In this setting, all eight channel data of the AD7768 is output only by the DOUT0.
Be
Figure 5. AD7768 outputs data to STM32F429 MCU SPI via DOUT0
issues that need resolving:
The AD7768 is used as a SPI host, so the STM32F429i SPI must be configured as a SPI slave.
High-level pulse is only a DCLK cycle, which is not typical.
After completing the output of all channel data bits, DCLK continues to output and is low.
Solution 1: MCU SPI as a slave, through a DOUT line and SPI host ADC interface
Configure an SPI port of STM32F429 (e.g., SPI4) to the slave, receives the data bits on the MOSI at the DCLK rate.
Connect the AD7768 to the STM32F429 external interrupt input pin Exti0 and NSS (SPI) pins. The rising edge will trigger the EXTI0 processing routine to enable the SPI slave to start receiving the data bit at the first DCLK falling edge after the low level. Timing design is critical here.
After receiving all the data of the channel 0 to passage 7, SPI should be disabled to prevent reading additional invalid data, as the SPI is changed to a low level, and the DCLK is kept switching.
Be
Image 6. AD7768 data bit reading in the timing solution
MCU firmware development precautions
When the software is in an interrupt mode, the DCLK running rate can be up to 4 MHz, and an ODR of 8 KSPS is implemented. The software should enter the interrupt handler and start the SPI within a semi-DCLK cycle (375 ns). To make the software easily enter the interrupt routine, the MCU can read data on the DCLK rising edge, thereby providing additional half DCLK cycle time. However, T5 DCLK rises to the DOUTX invalid minimum value to -3 ns (IOVDD = 1.8 V is -4 ns), so the propagation delay on Doutx (> | T5 | + MCU hold time) should pass through PCB wiring or buffer Increase.
Be
Figure 7. Configure SPI4 peripherals
Solution 2: MCU SPI as a slave, through two DOUT lines and SPI host ADC interface
In the first solution, only DOUT0 is used to output all 8 channel data. Therefore, the data read will limit the ADC throughput rate to 8 kSPs. As shown in FIG. 1, the channel 0 to passage 3 is output on the DOUT0, and the channels 4 to passage 7 are output on the DOUT1, and the data transmission time can be reduced. The connection of the serial line is shown in Figure 7. With this improvement, when DCLK is 4 MHz, ODR can easily reach 16 KSPS.
Be
Figure 8. The AD7768 outputs data to STM32F429 MCU SPI via Dout0 and Dout1
The firmware may not use the interrupt mode, and the polling mode is used to reduce the time delay that triggered from the rising edge to enable SPI reception data. This can achieve ODR of 32 kSPS at DCLK as 8 MHz.
Solution 3: MCU SPI as a slave, through DMA and SPI host ADC interface
Direct Memory Access (DMA) is used to provide high-speed data transmission between peripherals and memory and between memory and memory. DMA can quickly move data without any MCU operation, which can make MCU resources for performing other operations. Below is a design description of the MCU SPI as a slave receives data through DMA.
Solution 4: MCU SPI acts as a host and slave, read data by two DOUT lines
High throughput or multi-channel precision ADC provides two, four or even eight SDO lines for SPI ports to read code faster in serial mode. For microcontrollers having two or more SPI ports, these SPI ports can run simultaneously to speed up the code.
Be
Figure 9. Exti0 is in polling mode, SPI4 and SPI5 receive AD7768 data bits via DOUT0 and DOUT1.
Be
Figure 10. Exti0 is in polling mode, and SPI4 DMA receives the AD7768 data bits via DOUT0.
In the following cases, 32F429IDiscovery uses SPI4 as a SPI host, SPI5 as a SPI slave, receives EVAL-AD7606B-FMCZ data via DOUTA and DOUTB, as shown in FIG.
The AD7606B is a 16-bit synchronous sampling analog-to-digital conversion data acquisition system (DAS), with eight channels, each channel contains analog input clamp protection, programmable gain amplifier (PGA), low pass filter and 16-bit Approximation Register (SAR) ADC. The AD7606B also built-in flexible digital filter, low drift 2.5 V precision reference voltage source and reference voltage buffer, drive ADC and flexible parallel and serial interface. The AD7606B is powered by a 5 V single power supply, support ± 10 V, ± 5 V and ± 2.5 V true bipolar input range, all channels can be sampled at 800 kSPS.
Be
Figure 11. Use the MCU SPI to receive data through DOUTA and DOUTB in the master slave mode
Be
Figure 12. The SPI4 is configured as a host, and the SPI5 is configured as a slave.
Figure 13 shows the digital interface screenshot of Busy, SCLK, DOUTA, and DOUBs at 240 kSPS runtime.
Be
Figure 13. AD7606B BUSY, SCLK and oscilloscope screenshots of data on DOUTA and DOUTB
in conclusion
This article discusses the method of accessing ADCs with non-standard SPI interfaces using microcontroller SPI. These methods can be used directly, and can also be used to control the ADC SPI; they can be used as a SPI host or in combination with multiple DOUT lines to improve the throughput rate.
Be
Source Network
Our other product:
