"In order to meet the growing demand for near-field communication (NFC), developers need to quickly build optimized design. Traditional methods are slowed down, because designers should respond to various challenges, such as RF circuit optimization, NFC protocol management, Power consumption, and minimize design packaging.
In order to help developers overcome these difficulties, NXP and other companies have introduced IC and support hardware, providing a simpler way to add NFC functions.
This article will briefly explore how NFC evolve into the category of exceeding basic cash register (POS) applications. Next, this article will introduce NXP LPC8N04 NFC solutions and discuss how to use it to build efficient NFC design to support a variety of applications.
Why choose NFC
NFC has exceeded its original cash register to pay the application range, and developed into an important feature of various applications. Today, developers use smartphones and other mobile devices to NFC's universal support, simplify equipment control in consumer industry, industry and other fields.
Simply close your smartphone near intelligent toys, household appliances, or network devices, users can easily, securely configure and control the target system. Smartphone radio frequency field from the starter (called proximity coupled device, PCD) starts target (called proximity induction coupling card, PICC).
In this way, any PCD and PICCs that are compatible with ISO 14443 can use the data modulation amplifier to carry out two-way communication with the modulation and coding scheme specified in the standard.
NFC MCU
NXP LPC8N04 MCU provides a high-cost solution for NFC design. This 4 x 4 mm 24 pin MCU is based on the ARM® Cortex®-M0 + processor core, combines full NFC / RFID subsystems and serial interface, GPIO, memory, including 32 KB flash, 8 KB SRAM, and 4 KB EEPROM . The product itself has a low power consumption, which can be operated only by the acquisition of RF energy, and thus is ideal for use in an IoT-free connection system, a smart label in a stand-alone system, or any applications that need to optimize NFC solutions.
To simplify the development, the LPC8N04 integrates the ARM nested vector interrupt controller (NVIC) and serial line debugging (SWD). The SWD uses two observation points comparators and four breakpoint comparators, which can provide two-way data connections for JTAG testing and debugging, and provide runtime system memory access without having to add additional software on the device. In addition, the LPC8N04 firmware provides a full application programming interface (API) for erase the flash partition, copy data to flash, and read out the unique device serial number of the factory settings.
Of course, the key function of this paper is its NFC subsystem. The device is intended to support the growing application of NFC functions, which can provide complete NFC bidirectional communication capabilities through 13.56 MHz proximity signal transmission. The device is compatible with various NFC specifications, including NFC / RFID ISO 14443A, NFC Forum 2, and Mifre UltraLight EV1 PICC standards.
The subsystem provides a simple interface model for hardware and software connections (Figure 1). For hardware interfaces, the 50-skinned (PF) internal capacitance of the subsystem is compatible with standard NFC antenna, such as Molex 1462360021. Therefore, the developer can connect the ready-made antenna to the LA-LB pin of the LPC8N04. Also, the device can restore its clock from the radio frequency field without an additional clock element.
Functionally, all registers (CMDIN, DATAOUT, SR), and SRAMs used in NFC read / write operations are mapped to shared memory, and access is managed by an integrated arbitration unit. During communication sessions, external NFC / RFID launcher reads and write registers or SRAMs. Conversely, the firmware running on the LPC8N04 ARM Cortex-M0 + core will evaluate the register and SRAM, resolve information, and reply as appropriate use of the same shared resources. In order to protect the communication channel, the developer can use the MIFARE protocol password verification method, allowing or blocking access as needed.
The entire communication sequence starts when the radio frequency field transmitted by the external launcher is in the range of LPC8 N04. The RF field can be used to wake up the LPC8N04 from low-power sleep mode and use as its unique power supply as described below.
Power management
Power consumption is usually critical considerations for these applications. In the past, developers had to be compromised in function and performance in order to minimize power consumption. With LPC8N04, developers can use multiple device characteristics to coordinate power consumption and performance to meet the requirements.
In a typical method of reducing power consumption, developers typically modify system clock frequencies. By lpc8n04, developers can use this method to significantly reduce power consumption (Figure 2). At the maximum clock frequency of 8 MHz, the LPC8N04 consumes approximately 900 microam (μA) current. When the clock rate is reduced to 1 MHz, the power consumption will drop to 200 μA. In addition to adjusting the system clock rate, developers can also use a variety of different power modes to reduce power consumption by selectively shutting down certain parts of LPC8N04.
As most of the complex devices, LPC8N04 is assigned to different power domains to different power domains for circuits such as memory and analog external, digital cores, and peripherals, real-time clock (RTC), and undervoltage detector (BOD), etc.. (image 3). Conversely, the integrated power management unit (PMU) enables or disables low voltage difference (LDO) regulators powered by analog and digital power domain.
By setting the number of bits of the LPC8N04 Power Control (PCON) register, developers can program the PMU to control the power of these domains in three low power modes:
In Sleep mode, PMU maintains power supply of two domains - reducing power consumption, allowing fast recovery processor functions and instructions.
In depth sleep mode, PMU only disables analog domain - providing the maintenance processor status, peripheral register, and internal SRAM, but it is necessary to increase power-on time to access non-volatile memory.
In the depth power mode, the PMU closes the analog and digital domain, and the power consumption is reduced to only 3 μA, and the cost is the delay of the processor status and instruction execution recovery.
In all three low power modes, the PMU turns off the processor core. Therefore, using low power mode will increase the wake-up time required to return to full activity mode. Of course, the deeper the low power mode, the longer the wake-up time. But in fact, the wakeup time is enough for most NFC applications. Under the worst case, the total startup time from the open power supply to the power-on to reach the active mode is only 2.5 ms (MS).
RF energy collection
The LPC8N04 relatively fast wake-up time enables developers to collect energy from the actuator's radio frequency field from the initiator. When VNFC (voltage obtained from the radio field) rises above the threshold, the power selector in the power selection of the device automatically switches the device power from the battery mode to the captive energy (see Figure 3). Developers can operate LPC8N04 only by this power supply, or only use RF energy to collect power as a battery backup. Although the energy selector unit can automatically select the best power supply, the developer can force the VBAT or VNFC based on the application requirements.
In fact, the function of collecting RF energy is LPC8N04 depends on the intensity of the intensity of the radio frequency field emitted by the external reader, and the energy efficiency of the receiving antenna circuit connected to the LPC8N04. As previously mentioned, developers only need to connect the appropriate antenna to the LA-LB pin of the LPC8N04. But in fact, the ability to receive energy maximization depends on the design-optimized antenna circuit.
Whenever RFID / NFC design, the antenna inductance is formed to form a resonant circuit with the total input capacitance (antenna, receiver, and connection parasitic capacitance) of the radio frequency front end. The total resistance of the assembly determines the quality factor, which is related to the performance and field strength of the resonant circuit. For example, higher connection resistors reduce quality factors to reduce the effective transmission range of the RF transmitter.
Since the input capacitance and the input resistance are related to the input voltage (for LPC8N04 is VLA-LB), the design appropriate antenna is more complicated. When the input voltage is changed, the correlation change of the input capacitance causes the resonant frequency change, and the correlation change of the input resistance changes. Antenna design experts typically use minimum input voltages to deal with these changes.
Rapid development platform
Although the concept is simple, for the use of smartphone popular mobile phones with NFC functions, if developers want to quickly deploy applications, implementing high-efficiency NFC designs from heading will slow down their progress. By building on OM40002 development boards based on NXP LPC8N04, developers can instantly develop NFC applications immediately without having to create their own systems. A combination of LPC8N04 boards and related NXP software development kits provides a direct NFC solution, as well as platforms for building custom hardware design and software applications.
The OM40002 panel includes two parts, separated by removable interfaces (see the vertical line between the elements of Figure 4). The main processor (MP) portion includes an integrated antenna located at the top of the plate top (Fig. 4A, right) and the bottom of the bottom (Fig. 4B, right). The debug probe (DP) section includes NXP ARM Cortex-M0 LPC11U35FHI33 MCU and debugging resources (Fig. 4A, left). At the bottom of the DP portion (Fig. 4B, left), 5 x 7 LED array and surface mount speakers provide a simple user interface mechanism for example applications contained in the development kit. During development, engineers can use the entire system as a complete system. For custom designs, developers can use the entire development board to debug their application and can be removed later, serving as a stand-alone NFC subsystem.
The development board is pre-installed example application, and it operates as a firmware on the LPC11U35FHI33 MCU. With the LED array and speakers of the development board, the free Android app is provided and running a NXP, which shows how the LPC8N04 and how to support the NFC functions between the two-way NFC Data Exchange Format (NDEF) messaging. NDEF is used in most smartphones and other mobile devices with NFC functions, and is a lightweight format that can contain any data in a single message. By way of example Android applications, developers can more clearly understand the data types and sizes exchanged between the smartphone and the OM40002 board.
NDEF processing
In addition to the direct demo function, the example application provides developers with key design patterns that use LPC8N04 to process NDEF information. The NXP software development kit contains low-level service routines for handling register level transactions, while example applications are used to show high-level operations. The development kit contains the main routine to show the developer how to initialize the LPC8N04 hardware and related software structures before the main processing cycle.
When the first call is called, the main routine first tests whether it is due to the specific RTC event indicating that the wakeup counter has expired (WakeupReason == PMU_DPD_WAKEUPREASON_RTC). If not, the routine enters the primary loop, test the various instructions of the reader and perform the relevant operations to respond. If there is no NFC activity (for example, the smartphone is no longer in the range), the routine will eventually time out.
Although the concept is simple, the example application and the underlying service routine describe information processing using the NDEF of the LPC8N04. As shown in the list 1, the primary loop of the example application illustrates the operation sequence of processing NDEF information.
In normal operation, if a new NDEF message appears in the LPC8n04 shared memory, the interrupt is called, and the interrupt will set a tagwritten. In this signal-based architecture, the main routine is waiting until the amount of semaphore can be declared before loading information (NDEFT2T_GETMESSAGE) to its buffer. The routine reviews NDEF information (NDEFT2T_GETNEXTRECORD), extracts payload and resolves the result.
In this application, if the payload is a text string, the routine writes the data into the EEPROM (EEPROMWRITETAG) and enables the LED display (StartLepDisplay). If the payload is the value of the MIME type "Application / OCTET-stream", the routine checks the value of Bindata [0] to see if the data is music (Bindata [0] == 0x53) or scrolling speed adjustment (Bindata [0] = = 0x51). If the latter, the new scroll speed is saved to the EEPROM. If the former, the routine will extract the music data (EXTRACTMUSIC), write the data to the EEPROM, and if the user is running the music player, restart the music player (StartMusic).
The software suite provides all source code for this application and service routine. For example, developers can view the source code in the NDEFT2T_GETMESSAGE () and NDEFT2T_GetNextRecord () functions to learn more about reading and processing NDEF information. In many cases, developers may use the service routine directly without modification, thus focusing on the specific details of the application and the main () routine.
Summarize
Near field communication applications are constantly extending to more and more fields outside the cash register system. However, for developers, to minimize power consumption while optimizing radio frequency performance.A series of challenges involved Even for the most experienced engineers, it is very difficult.
By integrated full NFC subsystem, NXP LPC8N04 MCU eliminates most of the complexity of NFC design. For developers seeking fast solutions, NXP provides a completely useful sample application and a development platform based on LPC8N04, and a development platform, which is easy to build its own custom NFC solution.
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