First, wiring
(1) the wiring prioritize
Priority key signal lines: small-signal simulation key signal, the high-speed signal, a clock signal and a synchronization signal wiring density priority priority principle: start from the most complex devices wiring board connection relationship. From the board connection wiring densest area start point Note: a, the wiring layer is possible to provide a special key for the signal of the clock signal, a high frequency signal, the signal sensitivity, etc., and to ensure the minimum circuit area. Hand, shall take priority routing, shielding and to increase the safety margin or the like. Ensure signal quality. B, the environment is poor between EMC power and ground planes, are arranged to avoid interference-sensitive signals. c, impedance control requirements of the network should be requested by the wide wiring line LT.
(2) several specific alignment method
1, the clock wiring:
Clock line is one of the biggest factors for EMC. A clock line should be less hole played, and try to avoid running lines and other signal lines, and away from the general signal line, to avoid interference with the signal line. Board while the power supply portion should be avoided in order to prevent interference between power and clock.
If the board has a dedicated clock generation chip, which can not go below the line, shall be covered by the copper thereunder, where necessary, may be made thereto specialized cede territory. For many chips have the reference crystal oscillator, the crystal should not go below these lines to isolate plated copper.
2, alignment angle:
Right angle alignment is generally the case to avoid the PCB layout requirements, but also almost become one of the criteria to measure the quality of the wiring, then the right angle traces how much impact it would signal transmission? From the principle that the right-angle transmission line will take the line width changes, causing impedance discontinuities. In fact, not only is the right angle alignment, Dayton corner, acute angle traces may cause the impedance change. Effects of signal traces at right angles is reflected in three aspects: First, the corners may be equivalent to the capacitive load on the transmission line, slowing the rise time; two impedance discontinuities cause reflection signal; generating three right-angled tip the EMI.
3, differential traces:
Common differential signal and a single-ended signal traces compared, the most obvious advantage in the following three aspects:. A strong anti-interference ability, as good coupling between the two differential traces, when there is ambient noise almost simultaneously coupled to the two lines, but only the difference of the two signals concern the receiving end, the external common mode noise can be canceled completely. B. can effectively suppress EMI, the same token, since the two signals of opposite polarities, they may be external radiation electromagnetic fields offset each other, the more tightly coupled, the electromagnetic energy is released to the outside less.
c. Timing positioning accuracy, since change in the differential signal switch is located at the intersection of the two signals, rather than relying on ordinary single-ended signal level determining two threshold voltages, and thus subject to the process, a small influence of temperature, timing errors can be reduced , the circuit is also more suitable for low-amplitude signals. Popular LVDS (low voltage differential signaling) refers to such a small amplitude differential signal technology.
4, serpentine:
It is a kind of serpentine traces in Layout mode frequently used. Its main purpose is to adjust the delay, the system timing to meet the design requirements. First, the designer must know this: the signal quality will destroy the serpentine, the propagation delay change, to avoid the use of wiring. But the actual design, in order to ensure sufficient retention time signal, or to reduce the time offset between signals of the same group, often have to be deliberately winding.
Special note: paired differential signal lines, generally parallel lines, as little hole played, when necessary punch, should be perforated along two lines, in order to achieve impedance matching. A set of buses of the same properties, should be in parallel alignment, so as long as possible. The patch from the via pads drawn out from the pad farther as possible.
3) rules common wirings
1, the direction of alignment control rules:
I.e. alignment direction orthogonal to the adjacent layer structure. Avoid different signal lines in the adjacent layers go into the same direction, to reduce inter-layer crosstalk unnecessary; since the plate when the structural limitations (e.g., certain backsheet) is difficult to avoid this situation, particularly when high speed signals, isolating ground plane should consider the wiring layers, land-line isolation signal to each signal line.
2, the open loop alignment checking rules:
Generally does not allow one end of the floating wiring (Dangling Line) occurs mainly in order to avoid the "antenna effect", reducing unnecessary radiation interference and acceptance, it may cause unpredictable results.
3, check the impedance matching rules:
Wiring width should be consistent with the same network, the line width changes will cause uneven line characteristic impedance, when high transmission speeds will produce reflection, in the design should try to avoid this situation. Under certain conditions, such as lead connector, when the lead structure similar to the BGA package, and may change the line width can not be avoided, should minimize the effective length of the intermediate portion of the inconsistency.
4, the trace length control rules:
That short rule, in the design should try to make the wiring length as short as possible to minimize problems due to the interference caused by long traces, particularly important signal lines, such as clock lines, be sure to close the device from the oscillator on The place. Case of driving a plurality of devices, which the network topology should be decided depending on the circumstances
5, chamfering rules:
PCB design should avoid acute and right angles, unnecessary radiation, while the process performance is not good.
6, the device decoupling rules:
A. Increasing on the printed version of the necessary decoupling capacitors, filter interference signals on the power supply, the power supply signal stability. In a multilayer board, the position of the decoupling capacitors is generally not too high, but the double plate, wiring layout and decoupling capacitor power will directly affect the stability of the whole system, and sometimes even to the design success or failure. B. In the double plate design, should generally go through the filter capacitor current filtering device for re-use. C. in a high speed circuit design, the ability to properly use decoupling capacitors related to the stability of the entire board.
7, device layout partitioning / hierarchical rules:
A. mainly to prevent mutual interference between the different operating frequencies of modules, the wiring length as short as possible while the high frequency portion. B. mixing circuit, but also the analog and digital circuits are arranged on both sides of the PCB, using different layer wiring, with the intermediate formation isolated manner.
8, ground loop rule:
Loop minimum rules, i.e., the area of the signal line loop circuit comprising therewith as small as possible, the loop area smaller, fewer external radiation, receive external interference is also smaller
9, the power supply and ground rule integrity layer:
For vias dense region, to avoid holes in the interconnected power and ground hollowed area is formed on the division plane layer, thereby destroying the integrity of the plane of the layer, thus resulting in an increase in the circuit area of the signal line formation .
10,3W rules:
In order to reduce crosstalk between lines, line spacing should be large enough to ensure that, when the center line distance is not less than 3 times the line width can be maintained at 70% of the electric field do not interfere with each other, the rules referred 3W. To 98% of the electric field do not interfere with each other, the pitch can be used to 10W.
11, shielding
Rule corresponding to circuit ground, and indeed in order to minimize the area of the loop signal is more common in some of the more important signal, such as a clock signal, a synchronization signal; some particularly important, particularly high frequency signals, should be considered copper cable shielding structure design, line isolation is about to land around the cloth line, but also consider how to effectively combine well with the actual ground plane to shield effectively.
18,20H rules:
Since the electric field between the power layer and the formation is changed, electromagnetic interference is radiated outward on the edge of the plate. Side edge effect. The solution is to remove the power layer so that the electric field is only conducted within the range of the ground layer. In one h (the thickness between the power and the ground), 70% of the electric field can be limited to the side edge of the ground layer; the contraced 100h can be limited to 98% of the electric field.
Second, layout
Component Layout rules article N:
1. In accordance with the "first big small, first tackling the difficult" arrangement principle that is important unit circuit, the layout of the core components should be given priority. 2. Reference should layout block diagram, according to the main flow of the main components arranged law signal board. 3. The arrangement of components to facilitate debugging and maintenance, i.e., small element can not be placed around the large components, debugs the element, have sufficient space around the device. 4. The same configuration of the circuit part, as a "symmetric" standard layout; 5. Component same type cartridge should be placed in one direction in the X or Y direction. The same type of polarity should strive to maintain the consistent discrete components in the X or Y direction, to facilitate the production and testing. 6. Usually the heat generating element to be evenly distributed, and in order to facilitate heat dissipation board machine, the temperature sensitive device other than the temperature detecting element of a large amount of heat away from components. 7. The layout should meet the following requirements: the overall wiring as short as possible, the shortest key signal lines; weak high voltage signals, current signals and low current, low voltage completely separate; separate analog and digital signals; high-frequency signal separated from the low-frequency signal; high-frequency component to be spaced sufficiently. 8, the layout of the decoupling capacitors as close to the power pins of the IC, and the circuit formed between the power supply and ground to the shortest. Read the full text of the original title: PCB layout
Article Source: [Micro Signal: gh_7b9c8fb4c68a, micro-channel public number: Altium Designer learning] Add welcome attention! Please indicate the source of the article.
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