"Recent open source architecture, this topic is real fire, especially RISC-V, feeling there. Open source architecture is not a new thing, 丫 risc-v is playing?
The same is "open source", is there a different?
Speaking of open source instructions, Power and SPARC are often filed, but Power and SPARC have developed from the server and workstations, and the instruction set is relatively large. Go and see the Power's instruction manual [1], 900 provisions, using 18 pages, need to be very powerful, financial and accumulated vendors have the opportunity to achieve. This is not clear, it is to play this "open source" flag waiting for you to spend money to buy "technology transfer"? SPARC [2] Although there is no Power so complicated, the volume is not small. And so many years seem to play only SUN / ORACLE and a few vendors in playing, in the big background of IOE and other open source systems and databases such as Linux, the territory seems to be getting smaller and smaller. The open source core of the previous generation of Sparcv8 standards is indeed widely used in military space space, but they are rarely used in the consumer field, which is worth thinking.
Open source architecture has a new thing every few years, and then can always drive a group of domestic manufacturers to develop independent innovation processors, but this time is a bit different, where is it different? This is the domestic RISC-V participant, many of the private enterprises, the company's participation is also poor than the research institute. For example, Joining Le Xin, Zhongtian, etc. very early. Unlike several single seedlings funded by the state and local governments. Behind this fact is inevitably a profound industry and marketized business behavior.
What is the difference between RISC-V? The module has to mention, the simplest RV32i is only 40 instructions. If you want to function, you will use other instruction modules, just like a wooden wood, you should take it, you have to make it. A bit of a bit of college students can be a month [3], the difficulty has dropped, and there is a very powerful manufacturer, and many of the ability to do it yourself. Of course, this does not mean that RISC-V cannot do a large processor, with other instruction set modules, RISC-V can support floating point, vector operation, encryption, etc. This is the most unique place in RISC-V: can be extended.
Some people say that from a command set appeared to get a wide range of applications, for more than ten years. If it is a CPU that implements an IBM Power or SPARC or X86's instruction set, I think you are right, no more accumulative. But RISC-V is modular because it is simple enough because the opening source software is mature, because it can provide a complete ecology very early, it really has been made in just a few years. Take SiFive as an example, the Fe310 released last year is only an MCU-level chip. At the beginning of this year, 4 + 1 cores have been launched to run Linux's SOC.
Is it still important to debris?
Many people are worried about fragmentation, and they see the past ARM and MIPS in fragmentation, think that RISC-V's fragmentation problem will be more serious. Indeed, in order to prevent fragmentation, ARM strictly prohibit the user to modify the instruction set, which is certainly a certain extent. However, the idea of RISC-V solved is not strictly limited, just like Daxi, not to the barrier dam, relying on the guidance. This is reflected in the following aspects: First, the modular instruction set mentioned earlier allows the manufacturer to choose a standard instruction set in accordance with its own needs, and the vendor is not necessary to pay additional costs. Second, the instruction set reserved a large number of custom instructions, the command length supports from 16 bits to 1024 bits, which are dedicated to customized processor manufacturers to implement their own instructions. In this way, basic software can be compatible, encounter custom instruction sets, manufacturers provide a pre-design-wide-designed function library that can guarantee efficiency without loss of compatibility. It can be said that the ARM / Intel will not let you do it. Today, there is RISC-V, and your sister, you are bold to go forward.
In order to change, in the past, in the PC era, we are really worried about the adverse effects of fragmentation. Today, in the era of outbreak in IOT, we need a variety of customized processors and chips to complete data acquisition, low power, wireless communications, etc., many different work tasks. The more different demand, the more popular the open source tool, the smaller the impact of the upper software, the influence of the instruction set, the smaller the impact. Le Xin did not use the ARM instruction set of CPUs, which can make today's achievements sufficient to prove that the impact of fragmentation is not the main contradiction. This trend is very obvious, the times are different.
Directive set design is really not as simple as you think
At this time, you said, the RISC-V architecture is simple, the area is small, MIPS is not the same? In fact, in the CPU design, the instruction set seems to be the easiest, but in fact, it is the hardest thing to do simple things. On the one hand, RISC-V is late, after 5, this will make it absorb most of the lessons of many seniors fail, such as register window, long instructions, many pits have stepped over again . Also, don't look at the instruction set is the number of registers, branch jumps, Load / Store, etc., you can design a high-efficiency, code density, high instruction set, is not so easy. But so far, RISC-V This "college sent" instruction set is still very good. The X86_64 and ARMV8 do not phase under the indicator of the instruction density [4]. The instruction set can maintain a high level, and the technical capabilities of the latter vendors will not be restricted. They must know that their ability is the key.
Regarding the design level of RISC-V, David Ditzel should have the right to say, he was an early SPARC architect, and then created a company and called all the United States. I made a X86 CPU with the RISC architecture with the RISC architecture, once the Intel almost fell to the altar. This brother evaluated RISC-V in the past few years, the more playing, the more it is not simple, and the result of the final evaluation is nothing more than ARM / MIPS / SPARC [5]. After that, he made a high-performance RISC-V processor.
Money does not mention
After saying the technology, you have to talk about the money. Although these year ARM reduces the threshold in order to decrease, it is not low, Cortex-M0 and Cortex-M3, although they can use tens of thousands of US dollars to get authorization, but in turn to pay high royalty, but also To puminate according to the chip, the chip of M0 and M3 is mostly low cost chips, which directly affects the profit. In the past, you don't have a way, because you use some small CPUs, ecology is a big problem, the entire ecology behind ARM is an important endorsement. But RISC-V looks quickly to change this situation, and major third-party manufacturers have begun to support RISC-V, from commercial directive emulators to advanced debugging tracks. Apple, Gao Tong, Samsung, very early, I bought ARM architecture authorization, but you will find Qualcomm and Samsung have already joined the RISC-V Foundation very early. These large factories with self-developed CPU are not 5 years. I believe it. You can start your own RISC-V processor as the ecosystem is fully improved.
Many people think that it is always necessary for the CPU implementation based on this architecture. This is true, CPU IP vendors develop CPUs for different fields and sell them to intentional customers, and then charge the corresponding fees. But is this wrong with ARM? In fact, it is not entirely. Taking SiFive as an example, the current licensing fee is $ 30-500,000, which can get a core similar to M4-M7, but the ARM is different, as long as License Fee, the tax. But in fact, SiFive CPU Core's basic Rocket is completely open, although there is a small number of business versions, but for companies with certain technical capabilities, there is no problem based on this core customized.
A gratifying situation is that there is a large number of open source CPUs available on the market, and most of them are published in very loose and commercial licenses [6].
Where is the entrance of the second yuan?
Whether it is Intel or ARM, their success is by only because of technology. Intel is not just a FAB and R & D team that is proud of the group, and there is no Wintel Alliance these business decisions. ARM has made a low-power processor for decades, which can be defeated without creative IP nuclear authorized business models. If the next game will appear in the future, it will never move Intel and ARM's business model, which must be a significant advantage in the business model and technology progress.
Remember, you don't need "replace" Intel or ARM, once you find the entrance of the second yuan, then in this new order, there is no two objects of X86 and ARM at all.
"Choice" in the past
The experience and facts of years and research have told us that the relationship between the instruction set structure and performance is not big. Intel's X86 instruction sets many years ago will still prove this in the industry this year. The instruction set is the interface of software and hardware. It is an important ring in the compatibility level; however, from performance, the more complex and high performance processors, the smaller the influence of the instruction set, the smaller the impact . If you can recognize this, we will understand that RISC-V does not need to have too many technological innovations than x86 or ARM, as long as it provides a choice to the majority of manufacturers. What choice, a set of universal instructions, can suck up the technical progress of the past 30-40 years, and open, no barriers, costs that tend to 0. RISC is proposed in the 1980s and related studies have been mature. Standing in today's Moore Law, we need to spend more energy on the DSA architecture and agile hardware development, RISC-V plays the role of assists.
To flip over Thomas Friedman's "World is a flat" this book, "I believe that it is open, don't help with barriers", ARM, X86, RISC-V will still have a long time, but the high wall will be Smooth.
Rapidly mature ecosystem
The instruction set architecture is not expensive, and expensive is to open the up and down ecosystem. OpenRISC has been in the world because there is no high quality ongoing investment on the ecosystem, so it has not entered the main line of major toolchain for more than 10 years. RISC-V seems to be very similar to OpenRISC, but released in a short four years since 2014, it has been connected to the official main line by Linux / GCC / GLIBC / BINUTILS / GDB / QEMU. RISC-V can be used in only a few years of OpenRISC for more than ten years, without the promotion of all major manufacturers in the Foundation and the push of the foot and the earth. It can be said that the joint teams of these large and small manufacturers have their own strengths, completed all the work that the past IBM and Sun in the ecosystem, otherwise the ecological environment will not be so ripe.
With the rapid progress of the ecosystem, many manufacturers can get benefits from them; active communities and many open source cores, greatly reduce the development threshold of manufacturers; the active participation of manufacturers can continue to promote the development of the ecosystem, and finally Form positive feedback. In the face of a relatively low "live" instruction set, cooperate with the rapid mature ecological environment, for many domestic companies, as long as you have a need, there is a reason to participate.
RISC-V correctly open mode
A very common misunderstanding and thinking in the public is designed or produced CPU / MCU chip should be a company's main business, or a company with RISC-V must be selling CPU / MCU. It can be said that the market is indeed designed to manufacture MCUs for PC, mobile phones, and embedded areas, which is indeed one of the open modes of RISC-V. However, this RISC-V is a horn of the iceberg. We can see many companies. In their own field, through the embedding of a RISC-V CPU in their own products or solutions, improve flexibility, and ultimately improve their own Competitiveness. For example, NVIDIA replaces the custom processor of the internal use of Cadence, which is replaced by the RISC-V CPU you develop, soon, it will enter the next generation graphics card as the control core; CEVA has designed a use of its DSP communication solution. Low-power control processor; in front of Rambus, a RISC-V CPU is implemented in a solution in front of Rambus to protect system security.
Several examples show another important open way of RISC-V, which is to help companies in all fields to reduce costs, improve flexibility, thus improving their own competitiveness, which is the essence of business. Therefore, if "ask the right question" is a prerequisite for success. Then ask yourself: "As a company, what is your own advantage? Is RISC-V Have RISC-V Have you had the opportunity to help you improve your competitiveness?"
New era, there must be new ideas!
See:
• [1] Power ISA V3.0B March 29, 2017
• [2] Oracle SPARC Architecture 2015
• [3] College students design RISC-V CPU: Kamikaze, IFMRT RISC-V
• [4] Design of the Risc-V Instruction Set Architecture
• [5] Another Risc-V Religious Conversion
• [6] known RISC-V processor list
Original address: https://www.eeboard.com/news/risc-v-6/
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