The industry generally believes that mixed beam modes (such as Figure 1) will be the preferred architecture of 5G systems operating in microwave and millimeter wave. This architecture combines digital (MIMO) and analog beamforming to overcome high path losses and increase spectral efficiency. As shown in FIG. 1, the combination of M data streams is divided into the N-RF path to form beams in the free space, so the total number of antenna elements is the product M × n. Digital streams can be combined in a variety of ways, which can use high-level MIMO to guide all energy to a single user, or multi-user MIMO supports multiple users.
Figure 1. Mixed beamforming block diagram
This article will examine an example of a simple large-scale antenna array to explore the optimal technique of millimeter radio. Now go to the block diagram of the millimeter wave system radio part, we see a classic superherthe structure to complete the microwave signal to the digital signal, and then connect to the multi-channel RF signal processing path, which mainly uses a microwave moving phase and attenuator. To achieve beamforming.
Traditionally, the millimeter wave system is built with discrete devices, resulting in a large size and high cost. The devices in such systems use technologies such as CMOS, SiGe BicMos, and GaAs to enable each device to get better performance. For example, the data converter is now developed using CMOS process to enable the sampling rate to reach the GHz range. Up and down variable frequency and beamforming functions can be effectively implemented in SiGe BicMos. Depending on the system indicator requirements, it may be necessary to GAAS power amplifiers and low noise amplifiers, but if SiGe BicMos can meet the requirements, it will enable higher integration.
For 5G millimeter wave systems, the industry wants to install the microwave device on the back of the antenna substrate, which requires the microwave chip to be greatly improved. For example, the half-wavefall pitch of the antenna of 28 GHz is approximately 5 mm. The higher the frequency, the smaller this spacing, the chip or package size thus becomes an important consideration. Ideally, the entire block diagram of single-beam should be integrated into a single IC; in the actual situation, at least the upper and lower inverters and RF front ends should be integrated into a single RFIC. Integration and process choices are determined by the application, and we will experience this in the example analysis below.
Example analysis: Antenna center frequency is 28 GHz, EIRP is 60 dBm
This analysis considers a typical base station antenna system, and EIRP requires 60 dBm. Use the following assumptions:
Antenna Device Gain = 6 DBI (Aiming Line)
Waveform PAPR = 10 dB (using QAM's OFDM)
Power amplifier PAE = 30% at P1DB
Transmission / reception switch loss = 2 dB
Transmit / receive duty cycle = 70% / 30%
Data stream = 8
The power consumption of each circuit module is based on the prior art.
This model is built on the basis of 8 data streams, connects to different quantities of RF chains. The number of antennas in the model is expanded in an amount of 8, up to 512 components.
Figure 2 shows the linearity of the power amplifier varies with an increase in antenna gain. Note: Due to switching loss, the output power of the amplifier is 2 dB than the power supply to the antenna. When increasing the element to the antenna, the directional gain is raised as the X axis pair value is improved, so the power consumption requirements of each amplifier are reduced.
For convenience of explanation, we overlap the technical diagram on the curve, indicating which technique is best for different range antenna components. Note: There is a overlap between different technologies because each technique has an applicable value range. In addition, according to process and circuit design practice, there is also a range that can be achieved by specific technologies. When the components are very small, each chain requires high power PA (GaN and GaaS), but when the number of components exceeds 200, P1DB is reduced to 20 dBm or less, and the silicone can meet the range. When the number of components exceeds 500, the PA performance can be implemented in the current CMOS technology.
Figure 2. Relationship between antenna gain and power amplifier output level
Now consider the power consumption of the antenna TX system when the component increases, as shown in Figure 3. As expected, power consumption and antenna gain are relative relationship, but there is a limit. When more than a hundred components, the power consumption of PA no longer dominates, leading to the decline in benefits.
Figure 3. Relationship between the antenna gain and the antenna Tx part DC power consumption
The power consumption of the entire system is shown in Figure 4 (including transmitters and receivers). As in expectations, the power consumption of the receiver increases as the RF chain increases. If we will overlay the continuous decline in TX power curve on continuously rising RX power curves, we will observe a minimum power area.
In this example, the lowest value occurs when approximately 128 components. Review the technical map given in Figure 2, 128 components to achieve 60 dBm EIRP, optimal PA technology is GaaS.
Although the lowest antenna power consumption and 60 DBM EIRP can be achieved using GaAS PA, this may not meet all requirements of the system design. As mentioned earlier, in many cases, RFIC is required within the λ / 2 pitch of the antenna element. Use the GaAs transmit / receive module to provide the desired performance, but do not satisfy the dimensional constraints. In order to use the GaAs transmit / receive module, other packages and wiring schemes are needed.
Priority may be to increase the number of antenna elements to use the SiGe BicMos power amplifier integrated into RFIC. Figure 4 shows that when the number of components is doubled, the SiGE amplifier meets the output power requirements. The increase in power consumption is small, and the SiGe BicMos RFIC can be placed within the λ / 2 pitch of the antenna element (28 GHz).
Extend this practice to CMOS, we found that CMOS can also achieve overall 60 dBm EIRP, but from the technical map, the number of components must be doubled. Therefore, this scheme will result in dimensions and power consumption, taking into account current technology limits, CMOS methods are not a feasible choice.
Figure 4. Relationship between DC power consumption and antenna gain of the entire antenna array
Our analysis shows that when considering power consumption and integrated dimensions, the best solution currently implemented 60DBM EIRP antennas is to integrate SiGe BicMos technology into RFIC. However, if considering the lower power consumption antenna for CPE, CMOS is of course a feasible solution.
This analysis is based on current available technologies, but millimeter silicon process and design technology are making significant progress. We expect future silicon processes to have better energy efficiency and higher output power capabilities, which will enable smaller sizes and further optimize antenna size.
With the increasingness of 5G, the designers will continue to encounter challenges. When determining the best technical solution for millimeter wave radio applications, it is beneficial to consider all aspects of the signal chain and the various advantages of different IC processes. As 5G ecosystems continue to evolve, Adi recommends the unique bit to millimeter waveability, which is committed to providing customers with a wide range of technological portfolios (including various circuit design processes) and systematic methods.
Original link: https://www.eeboard.com/news/5g-18/
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