PCIe bifurcation - avoid access to Intel access data streams

Invea-Tech and CESNET (Czech Republic National Research Institute and Education Network) demonstrates a method that uses two FPGA PCIe Gen 3 × 8 interfaces to maintain data transfer from 100Gbps Ethernet ports to CPU hosts. This concept is called bifurcation, which is introduced in Intel Core I7 CPU a few years ago. Intel Attempts to allow 16 ports of the CPU's PCIE to handle two separate tasks, of course, in the opposite mode, such as combining two external PCIE8 ports into a 16-port. Use bifurcation to establish a 100Gbps system on a single FPGA, which eliminates the need for additional PCIE switching chips, saving costs, spatially and about 6W. CESNET and Invea-Tech have conducted a series of experiments to show the benefits of PCIe bifurcation. The test program includes the FPGA card loaded with a piece of Sailive Virtex-7 H580T 3D FPGA. Two FPGA PCIE X8 PCIe X16 card slots on the hard block access card. The FPGA firmware running the Linux device is transmitted to the annular buffer located in the PC RAM. The PCIe X8 interface uses Round-Robin to transfer data to a single cache. The block diagram below shows the experiment process: In the flow rate of more than 100Gbps generated in FPGA, a random packet data generator is exemplified. The following figure shows the result of the transmission rate: The DMA engine is disconnected in the FPGA group, so the packet length does not affect the original PCIe throughput. The achievable throughput is 107 Gbps. Note that at least 8 CPU cores are required for smaller packet scaling processes to achieve the goal 100Gbps. Read more

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