"Current situation of semiconductor testing industry"
The electronics industry is under constant pressure to reduce its manufacturing costs. The time to market put a lot of pressure on semiconductor manufacturers. The profit was the highest in a short time after new products were put into the market. Then, due to competitors developing similar base price products, the profit level began to decline. Developing an effective cost-effective test program is often the bottleneck that hinders the mass production of new products.
For semiconductor suppliers, the test cost has been regarded as no "value-added" cost. As shown in Figure 1, the percentage of capital cost in the average selling price (ASP) of IC gradually decreases - From 5% in 2001 to about 1% in 2010. However, the ASP of the overall device is also decreasing, which means that in terms of absolute cost, the test cost needs to be reduced at the same or greater rate as the reduction of device ASAP, which makes the test engineers face greater pressure to find more cost-effective test solutions.
The reality is that traditional or "big" can be improved by using techniques such as parallel testing (also known as multipoint testing) ” The utilization of test system will only produce limited improvement in test cost, but does not really solve the core problem of test system cost. For the testing needs of development laboratory, fault analysis laboratory or small batch production, the multi site testing strategy will not improve the economy of testing.
Today's semiconductor devices include various digital, memory, analog, mixed signal and RF modules, all of which are integrated in a single package or SOC (system) on Chip, system chip). As a result, the test solution must not only be cost-effective, but also flexible to meet the test requirements of a range of circuit types including logic, memory, analog, MEM and RF modules. Test solutions should be able to provide engineers with the ability to cost effectively automate design verification, fault analysis and pilot production test activities without using expensive "big" ”。
The challenge for today's test engineers is to create new test methods and systems, which can significantly reduce the test cost and solve the requirements of configurable and flexible test solutions. Compact based PCI Extensions for The latest development of digital, analog and RF test products and systems enables test engineers to use the platform to meet the test requirements of a series of ate equipment. In particular, digital products provide the function of parameter measurement unit (PMU) per pin, and now provide ate semiconductor test function with high value and performance. In addition, PXI test system provides cost-effective ate for test engineers, which can be used for fault analysis, prototype equipment verification and test / early production operation - Allow "big" "Iron" ate focuses on mass production test applications while providing engineering test functionality in a compact and configurable platform.
Semiconductor test requirements
The basic test requirements of digital and mixed signal devices include DC parameter test and function test. For DC test, the pin of the device must be characterized, and a PMU (parameter measurement unit) is required. If a single PMU is used, the pins of all devices accessible through the multiplexer switch are required to realize the excitation voltage / measurement current or excitation current / measurement voltage. Once the DC parameter test is completed, the functional test of the device can be performed. In this case, a digitizer with deep enough memory, programmable per channel (voltage, load and direction) and real-time comparison becomes the key to perform functional test. The basic configuration for solving these functions is shown in Figure 2.
As shown in Fig. 2, the combination of a single PMU, switching network (multiplexing) and digitizer quickly becomes cumbersome and performance limited for medium to high pin count devices. In addition, the combination of switching time and programming / measurement time for DC test can easily take 10 or even 100 milliseconds, and the time for DC parameter test will become very long.
A better solution and professional ate or "big" The "iron" system usually uses one PMU per pin or channel to provide outstanding test performance (including speed and measurement accuracy). Figure 3 details the architecture of the digital instrument of the PMU configured per pin.
Today, the gx5295 of marvintest's semiconductor test solution has a 32 channel digital I / O and PMU per pin architecture can be used as part of a compact PXI test platform, such as ts-900 semiconductor test system - Provide users with multi-channel number and digital Mixed signal test system and has a small, compact PXI chassis floor area.
DC parameter test
As mentioned earlier, PMU can use one of two modes to perform DC characteristic test on input and output lines of digital equipment:
§ Forced voltage / measured current
Using this method, the PMU applies a constant voltage and uses its on-board measurement capability to measure the current drawn by the tested device / pin. It can also measure the voltage provided by the PMU.
§ Forced current / measured voltage
Using this method, the PMU forces a constant current to flow through the device or absorbs a constant current from the device pin, and then measures the voltage. It can also measure the perfusion current / source current of the PMU.
By combining the PMU and digital test function of each channel in one instrument, a series of DC tests on digital and mixed signal devices can be significantly simplified. Common DC tests performed on semiconductor devices include:
n VIH: (high level input) the minimum positive voltage applied to the device input, and the device will be accepted by logic high
n VIL: (low level input) the maximum positive voltage applied to the device input, and the device will be accepted by logic low
n Vol: (low level output) the maximum positive voltage output by the device is defined as the maximum low positive level under the "guaranteed" specified load current
n Voh: (high level output) the minimum positive voltage output by the device is defined as the minimum high positive level under the "guaranteed" specified load current
n IIL: (low level input leakage current) the input leakage current measured when the input is logic low level
n IIH: (high level input leakage current) the input leakage current measured when the input is logic high level
n IOS (H): (high-level short-circuit output current) output is the short-circuit output current at logic high level
n IOS (L): (low level short-circuit output current) the short-circuit output current when the output is in the logic low state
Example: Voh, Vol and IOS test
The output voltage level test is used to verify the operation of the digital output when used under specified load conditions. They can also be used to simulate worst-case load conditions to observe the operation of the DUT when the output load exceeds its specified limit (e.g. when short circuit to ground). When performing these types of tests, the test current range that will not damage the device under test (DUT) shall be selected to fully test the output.
The following example shows how to perform a Voh test on a digital output. The purpose of this test is to ensure that the DUT maintains an output voltage higher than its specified output high level while providing its maximum rated drive current. For this test, the PMU is programmed to absorb current from the DUT to simulate load conditions. Figure 5 shows the connection between the DUT and the digital instrument.
To perform this test, the DUT is powered on and a channel of the instrument (ch1 in this example) is used to apply an input logic level that forces the output of the DUT to be logic high. Note that each instrument channel can be configured as a PMU or digital I / O mode, which provides the required flexibility and functions to support Voh, Vol and IOS tests. These tests require that the output of the device be programmed to the correct state before PMU measurement.
The second digital channel (CH2 in this example) is set to PMU forced current / measured voltage mode, and the initial current absorption value will not damage the DUT output pin. Then, the PMU is programmed to make the device current from minimum to maximum test value. At each test current value, measure the output voltage of the DUT to ensure that it is within the specified voltage range of logic high level. The actual PMU test current can also be measured and used to provide a load to output voltage level curve for each (see Figure 6). In this case, the device under test (DUT) is an octal latch, and each output tests the output level and current load.
The above testing techniques can also be used for Vol and IOS testing. For Vol test, the output of the DUT will be programmed to logic low level, and the output will be applied to the specified load of the output when measuring the output voltage level to ensure that it is within the specification range of the device. For IOS parameters, the output will be programmed to the specified logic state, which is applied to the output short circuit and the measured result current.
Examples: leakage current test (IIL, IIH) and V-I test
The inputs of the test device include a leakage current test and a protective diode characterizing each input of the DUT. These tests are performed by gradually applying a constant voltage to the DUT input pin and measuring the input current at each step (Figure 7). Since the leakage current is usually in the UA range, the PMU should be set to a more sensitive current range to achieve more accurate measurement.
To perform the leakage current test, the DUT will be powered on and the PMU pin will be set to forced voltage / measured current mode. At each input voltage setting, the PMU measures the current drawn by the input and then verifies the value according to the DUT specification. The actual test voltage being collected by PMU can also be measured. The test techniques shown here can also be used for VIL and VIH tests.
For measuring / characterizing the input protection diode pins connected to the device and ground and VCC, the PMU is configured to force voltage / measure current, where the voltage is sequentially stepped in small increments to produce a V-I curve for each diode. Figure 8 shows the V-I curve of the protection diode of TTL digital device. Note that the device begins to turn on at a junction voltage of about 0.4 v.
Semiconductor test automation
Today's test engineers are under constant pressure to shorten test development time and become more efficient in creating test programs. Combined with software tools that can automatically create and execute equipment tests, the test development framework provides a powerful software development environment for test engineers to improve the productivity of test development and deployment. For example, ts-900 of Marvin test solution includes ateasy - A fully functional test execution environment for managing program development and deployment, and a test library that simplifies the creation and execution of standard tests. It provides interactive tools for drawing IV characteristic curves and supporting two-dimensional shmoo diagrams.
DC parameter automatic test creation
Iceasy's library includes a complete set of test functions to characterize the input and output DC characteristics of the device. Using the PMU per pin function of ts-900, users can quickly create test programs for the following types of tests:
§ Openand Shorts
§ Input Leakage ( IIL, IIH)
§ Input Voltage Threshold ( VIH, VIL)
§ Output Short Circuit ( IOSH, IOSL)
§ Output Voltage Threshold ( VOH, VOL)
§ Power Consumption ( IDD, IDDQ)
These preconfigured tests combine the device pin and pin group mapping function of iceasy, providing users with a simple and simplified method to assign specific device pins to tests and specify the pass / fail limit of each test without performing low-level instrument settings and control. The result is faster test creation and shorter test time.
I-V Curve Tool
Current of iceasy - The voltage (I-V) curve tool enables the user to graphically plot the I-V characteristics of the ESD diode of the device. This test method can deeply understand the device fault mechanisms that may affect the device I / O pins, such as electrical stress (EOS), electrostatic discharge (ESD), bonding wire problems and packaging problems. Moreover, recently, the use of I-V curves as "impedance characteristics" may help to identify counterfeit products, in which the impedance or I-V labels of known real parts are compared with suspicious parts.
Iceasy's I-V curve tool allows users to easily set voltage and current ranges and step increments, and define specific pins (or pins) to be tested by name. In addition, all I / O pins can be drawn on the same graph, providing a simple way to compare the I-V curves of all devices. ( See Figure 9) the drawing data can also be easily exported through the test execution environment (ateasy) of ts-900. The ability to easily measure I-V characteristics and draw results is a key feature in fault analysis and design verification applications.
Shmoo Plot Tool
Iceasy's shmoo drawing tool allows users to easily change test parameters on the X and Y axes without programming - It allows the test engineer to visually observe the pass / fail operation range of the tested equipment. The shmoo drawing function of ts-900 is a recognized test method for equipment characterization and identification, and provides users with powerful design verification and early production test qualification technology. Iceasy's shmoo tool supports automation and interactive control, allowing users to change parameters immediately or control tests and record generated data through ts-900's test manager (ateasy). As shown in FIG. 10, the shmoo tool allows the user to easily change the range of test parameters, such as VCC, clock frequency, edge placement, input level, etc., in order to fully characterize the pass / fail operating conditions of the device.
PXI semiconductor test system
Considering the availability of instruments and software to meet semiconductor test requirements, test engineers can now choose to adopt PXI architecture to meet current and future ate requirements. Systems such as the ts-900 provide comparable functionality and performance for proprietary ate systems. Today, up to 512 digital I / OS can be supported in a compact 20 slot PXI chassis using 16 32 channel gx5295 digital I / OS (with PMU per pin) / O channel.
In addition, through standardization on PXI platform, users can expand the system by combining various instruments including SMU, digitizer, AWG, RF signal source and analyzer.
With integrated high-performance modular receiver interface, ts-900 is an ideal platform for users to optimize the overall test strategy of product life cycle. As shown in Table 1, ts-900 has significant advantages as a new product compared with manual or semi-automatic desktop test configuration. Using test systems such as ts-900 can provide engineers with a faster and more automated process for characterizing devices, thus shortening device characterization and verification from weeks to days. In addition, ts-900 can effectively solve the test cost of early production equipment without maintenance
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