"Although semiconductor technology is the foundation of all electronic products, it is a software that truly achieves modernization. Compared with hardware, software provides almost unlimited flexibility, and when the software runs on high performance microprocessors It may produce an amazing result. For example, if it is not running software on the latest processor, artificial intelligence is impossible to make progress.
In the past few decades, the balance between hardware and software has changed. It is widely believed that there are now about 70% of the product feature is defined in the design of the embedded software, which is almost entirely in its flexibility.
However, as the application pushes the performance, this imbalance has become a constraint. Software is based on abstract forms, accompanied by inevitable overhead in implementation time. The same functionality implemented in the dedicated hardware of the transistor level is always faster. This performance gain is usually at the expense of flexibility, but it is benefited from a device integrating three key technologies (handling kernel, fixed functions, and reconfigurable hardware), and implements the correct balance between performance and flexibility. It has become easier.
High performance optimization solution
Devices integrated with the above three techniques are often referred to as a chip system (SOC). In essence, they collect all the advantages of these functions into a single platform, providing greater flexibility than fixed-function devices, more configurable than microcontrollers, and more functional diversity than FPGAs. .
For several reasons, this integration is a good combination for applications. Performance is a major reason that can be interpreted as throughput or real-time response. Design of low power and optimization may be another reason. The more functions that can be integrated on a single device, the less the external components required. These scenarios include two "turning points" of the SOC, which enables pure performance scenarios and scenarios to optimize design.
If the throughput is the ultimate goal, the performance provided by the full-specific design in the form of ASIC will be difficult to surpass. However, although NRE costs are declining, it still needs to be based on the cost of development of ASICs, and the number is usually only commercial value in large quantities. For a long time, FPGA technology has been providing the industry as a performance as ASIC in a platform that is still configurable after a device is left. Bottom technology uses the query table to simulate full custom logic, but there are always some hardcutive integration, especially when the function is not easy to simulate in logic. Recently, this technology has developed and has included the processor subsystem, so that these devices are also undoubted into the SOC category. The FPGA industry leaders provide a device that perfectly binds three SOC key components. These include Xilinx Zynq® UltraScale + Series, which provides devices with two or four ARM® Cortex®-A53 kernels and ARM Cortex-R5 kernels.
These devices are for high performance applications, and the SOC that belongs to the second category includes the Microsemi's SmartFusion2 SoC FPGA Series and the PSoC 5LP series of Cypress Semiconductor. Both devices integrate ARM Cortex-M3 kernels and hardware features and configurable hardware. All devices mentioned here are supported by the platform, which simultaneously provides comprehensive support for application development in hardware and software levels.
Multi-core SOC
Xilinx's ZCU 102 evaluation board uses Zynq UltraScale + XCZU9EG multiprocessor SOC to provide incredible high integration. Its multi-core processing features include a Cortex-A53 64-bit quad-core processor and a Cortex-R5 dual-core real-time processor, closely coupled to FPGA logic, connection interface, and graphics processing unit (Figure 1).
The evaluation board (Fig. 2) has a 4 GB DDR4 SODIMM connected to the processing subsystem and another 512 MB DDR4 memory connected to the programmable logic. It also includes two FPGA clamp card (FMC) interfaces for further expansion (PCIe Gen2x4, USB3, display port, SATA), providing ideal assessments for various applications in automotive, industrial, video, and communications. platform.
The EG series system logic units are extended to more than 100,000, and the number of logical blocks (CLB) query tables (LUTs) is from about 50,000 to more than 500,000. With this level of configurability and enhanced multimedia blocks and integrated high-speed peripherals, the Zynq UltraScale + series can be used in a variety of requirements. The ZCU 102 evaluation board is an ideal platform for developers, which provides up to five times per watts of performance compared to the Zynq-7000 series.
Application example
People have increasing the requirements of performance, which is most obvious in communication. Most of the Internet activities involve information stored in the database, the most common database is SQL. A technique for accelerating SQL databases is to use a cache memory, which is usually implemented using a standard processor with integrated DRAM.
Although this approach can work, it is also bound by the processor architecture because the processor architecture is not designed for such applications. Devices such as Zynq UltraScale + can provide optimized solutions for streaming data, without affecting the processor because all advanced features of the processor make it as far as the independent server in the network. Measure according to standard X86 processors, which makes it four-fold, while power consumption is reduced by 20 times.
In the automotive industry, the use of ADAS will be further increased because the vehicle camera is used. This will give the demand for the SOC capable of processing up to six 30-frame / sec frame speed 2 megapixel camera. With its highly integrated features, Zynq UltraScale + is ideal for this challenging application.
ZCU 102 is equipped with all the tools and IPs required to start development and more other applications. It also includes a Vivado Design Suite: Design Volume Code (with XCZU9EG on the evaluation board for node lock and device lock).
SOC in the Internet of Things
Internet of Things is commonly described as a device network with limited resources and functions, but it also involves many existing applications and automation. With its highly integrated features, it is possible to provide an ideal platform for proper functional levels and low power SOCs.
For example, Microsemi's SmartFusion2 is for motor control and industrial automation, but it can also lay the foundation for secure connection devices. It integrates flash-based FPGA structure with ARM Cortex-M3 kernels and high-performance communication interfaces (including CAN, Gigabit Ethernet, HS-USB, and PCIe), and DDR2 / DDR3 memory controller. In order to support application development using SmartFusion2, Microsemi has developed a SMARTFusion2 senior development kit. The main characteristics of the evaluation board are shown in Figures 3 and 4.
MicroSemi has developed a demo application with this suite to provide all the software and support required to create a security web server (supporting the use of TLS / SSL security protocol sent and received); this app is currently deployed in the Internet of Things Application.
As shown in Figure 5, the application layer receives a request from the client browser and responds with a static web page, and the server is run on SmartFusion2. The TLS / SSL protocol is implemented using open source library Polarssl. Transport layer (TCP / IP) is implemented by more open source software, which can be used without operating system. In this example, the FREERTOS open source real-time operating system determines the priority of the task and schedules tasks. This advanced development kit can also be configured to run UCLinux, which is based on the Linux kernel modified by Microsemi for SmartFusion2 SOC.
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SmartFusion2 has 150,000 logical components, a 166 MHz Cortex-M3 kernel and a dedicated DSP block, plus embedded NVM (non-volatile memory) and SRAM, good in configurability and hard work function balance. This advanced development kit takes this potential with the PCIe edge connector, FMC connector, two Gigabit Ethernet ports, SPI, and UART support. With new high-performance operational amplifiers, the power consumption of devices can be measured during the development process, helping developers design the best solution within a given power budget.
Optimized design
Single-chip solutions are widely used in various applications, and digital devices, analog devices, and memory are integrated and integrated together to provide optimized custom devices. This can always reduce the PCB area, reduce the number of external components and reduce the BOM cost.
Programmable analog devices are much less more than the corresponding digital devices, and can be said to be based on the PSoC series of CyPress Semiconductor. PSoC device (ie, programming SOC) uses microcontroller kernel, hard work block, and programmable logic, which distinguishes it to use the switch capacitor technology, operational amplifier, comparator, ADC, and DAC and digital filter module configurable simulation Peripheral. These characteristics work together to create a configuration of complex analog signal paths that are tightly coupled to digital functions on the chip.
The CY8CKIT-050 development kit can be used in conjunction with the PSoC Creator Integrated Development Environment (IDE), based on PSoC 5LP development. The main components of the development kit are shown in Figure 6.
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PSoC Creator is a distinctive IDE; it can be used in parallel to develop embedded software implemented in the configurable simulation blocks of the device (in this example, running on the ARM Cortex-M3 core of PSoC 5) and hardware features. You can use the drag and drop to add analog function to your design, dynamically generate the API to access these features through software. IDE comes with a large number of predefined amplifiers and filters, but also allows developers to create their own functions.
In order to demonstrate the function of PSoC 5, CyPress creates a large number of application examples, including examples that implement the solar micro-inverter controller. Figure 7 shows an architectural overview of the application. Micro-inverters involve several conversion stages, including ripple elimination boost control, output current control, phase locked loop control, and maximum power point tracking algorithm. This application can properly demonstrate the function of the platform.
Summarize
Although software can provide abstract ways to achieve almost all tasks or features, there is little transcendence hardware in terms of performance. As people increase the demand for higher throughput and higher configurability, the platform combined with hardware, software, numbers, and simulation is also becoming more and more feasible.
These SOCs can meet the needs, but as in any implementation, some compromises need to be made. Not all SOCs can provide appropriate hard work. Inevitably, no application is likely to take advantage of all available features, and in some cases, the cost of cost-effective platforms may be too high, so that it is unbearable.
However, with the development of technology, these compromises have become less obvious, and the flexibility they provide is likely to provide reasons for their use in wider applications. "
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