Renesu Electronics recently released the high-end product "R-Car H1" of the in-vehicle information terminal with SOC (System On A CHIP). The equipped CPU includes 4-core version "Cortex-A9" and "SH-4A" total 5 cores, integrated with high performance three-dimensional drawing circuit (GPU), image recognition engine, support 1080P video decoding multimedia processing circuitry, and various interfaces Circuit, etc. Sample delivery from November 2011, starting from December 2012. This product is manufactured using 45 nm process technology for TSMC.
Renesa has changed the vehicle information terminal to "R-Car" since 2011, providing "R-Car E" facing the entry-level terminal (see this station report 1), "R-Car" for the mid-range terminal M ", as well as three products for" R-Car H "for high-end terminals. After the R-Car H1 released, three products were complete.
According to Renesa, the reason for developing R-Car H1 is to consider the following functions as high-end in-vehicle information terminals before and after 2013: (1) Multiple application processing can be made synchronously, (2) enable high texture And comfortable inventory, (3) play high quality image and audio, (4) can provide support for the driver via image identification.
The CPU part of the R-Car H1 is 4-core Cortex-A9 (10,000 MIPS (press DHRYSTONE)), and the maximum running frequency is 800MHz (1760MIPS (press DHRYSTONE)) constitute. Cortex-A9 performs application processing software using General OS, SH-4A performs real-time processing software using real-time OS. Hardware mechanisms that can be controlled to all systems access storage areas and peripherals.
The GPU part uses "PowerVR SGX543MP2" for three-dimensional graphics processing, as well as the "Rissa graphics processor" for two-dimensional graphics processing. According to Renesa, the actual capacity of dual-core SGX543MP2 is 40GFLOPs, and 83 million polygons can be processed per second. The purpose is to smoothly displays a high fine stereo map and an operation screen using a three-dimensional graphic.
The multimedia processing circuit has a video decoding function that supports 19201080 pixels, 60 frames / sec video, which converts the interleaved image to progressive imaging and performing brightness correction, etc., and supports audio playback function of 7.1 channels, etc. .
The image recognition engine uses Rissa's "IMP-X3". The engine is achieved by reforming the "IMP-X2" equipped with LSI "SH7766" (report 2) released on October 13. 4 processes can be performed in parallel, including the identification of the lane and the identification, the pedestrian and other vehicles, and image recognition processing such as identification of the operator gesture.
Renesa also improved the delay in preventing multi-core parallel processing. First, the memory bandwidth is expanded by equipped with a dual channel DDR3 memory interface circuit. This can be separated, such as the Cortex-A9 and the GPU use a channel of DDR3 interface, while the SH-4A is using another channel of the DDR3 interface using another channel. According to the company, the DMA controller to 46 channels also contributed to the number of reducing memory access. In addition, by increasing the internal bus speed, and the multilayer structure allocation method of improving the bus, the maximum processing performance caused by internal bus performance is reduced. Technology area
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