"More and more designs are developing towards mixed signals. IBS predicts that 73% of all integrated circuit designs will be mixed signal designs by 2006. At present, mixed signal technology has become a hot topic in EDA industry. With the development of deep submicron and nanotechnology, chip design and manufacturing has changed from single IC and ASIC to SOC. Now SOC has also changed from digital SOC to hybrid SOC, becoming a real system level chip. Mixed signal design can reduce the cost, reduce the overall size of the circuit, and provide better functions.
Chip verification accounts for 50% to 70% of the workload of chip design, and a lot of manpower, hardware and time resources are consumed in verification. With the increase of chip complexity, the verification work is increasing exponentially in both complexity and workload. Therefore, verification technology is the key of mixed signal technology.
It is difficult to clearly distinguish between analog chips with a few digital functions or digital chips that can realize some analog functions and mixed signal chips. Even in the process, more and more analog chips use CMOS process to replace the traditional BiCMOS process. The standard of mixed signal integrated circuit should be that it has important functions in both digital and analog, not simply some analog circuits embedded in digital chip or some digital circuits embedded in analog chip.
For Chinese IC designers, although the concept of mixed signal design has existed for a long time, there are not many technologies that really use mixed signal design. Most of them only use traditional methods, such as writing the digital part in HDL, and then carrying out simulation, synthesis, layout and wiring; The simulation part draws the circuit diagram and uses SPICE simulation to design the layout; Splice the two parts together. The real mixed signal design needs to combine digital and analog, make overall consideration and verification, and need more flexible design ideas.
Mixed signal SoC design faces such challenges: the mixing of behavior level digital and transistor level analog, the mixing of HDL language driven digital and schematic diagram driven analog, and the mixing of top-down digital and bottom-up analog. It is no longer the traditional digital design or traditional analog design, nor the simple superposition of digital design and analog design. Mixed signal design puts forward a new design concept, and a new design process must be used.
ADMS solution
EDA company has been fully aware of this technical demand, and its three major suppliers - mentor graphics, Synopsys and cadence began to integrate or develop analog and mixed signal tools and technologies a few years ago. Next, we take advance MS (ADMS), a hybrid verification platform of mentor graphics, as an example to illustrate how it solves the problem of mixed signal design.
Before understanding ADMS, let's take a look at several EDA design tools related to ADMS.
1. HDL simulation tool Modelsim
Modelsim is a current digital simulator, which has long been familiar to Chinese users. Its mature technology is well known, so it will not be introduced in detail here.
two SPICE simulation tool Eldo
The important part of analog circuit design is circuit simulation. The full name of spice is simulation program on IC emphasis. It was founded by the University of California, Berkeley in the 1970s. Since then, it has become a classic method of circuit simulation. Now, spice method is basically used in circuit simulation. Spice program is open source, and various popular versions of spice are derived from UCB spice. HSPICE was developed in 1981 and is a successful commercial spice. Eldo is a rising star of spice in recent years. Its R & D team is located in France. Basically, the spice used in the design is Eldo in Europe. Recently, Eldo has also begun to be promoted in North America and Asia.
A simulator can be evaluated from the aspects of accuracy, speed, capacity, convergence, control interface, function and the support of process manufacturers.
, accuracy. Eldo carries out global check through Kirchhoff current constraint, strictly controls the convergence and ensures the convergence. Eldo adds OSR and IEM algorithms in addition to Newton Raphson (i.e. NR) algorithm used in traditional spice. The new algorithm makes Eldo more efficient than traditional spice.
Second, speed. The new algorithm used by Eldo also increases the simulation speed, which is 3 to 10 times that of the general spice. Eldo can also adopt different algorithms for different circuit sub modules. For example, it adopts the much faster OSR algorithm for digital circuit modules, which greatly improves the speed. In particular, Eldo itself supports behavior level description. In this sense, Eldo is not only a spice, but also a hybrid simulator.
Third, capacity. Eldo can simulate large-scale circuits, up to 300000 transistors.
Fourth, convergence. In terms of convergence, Eldo adopts advanced technologies, such as the segmentation concept introduced by DC convergence (automatically segment and recombine the circuit when it does not converge, and change the matrix), so as to improve the convergence.
Fifth, control interface. Eldo is fairly simple to use. Eldo can be used alone (i.e. command line mode) or integrated into the circuit diagram editing tool environment, such as Da IC of mentor graphics or schematics composer of cadence. Eldo's input file format can be standard spice or HSPICE. In fact, HSPICE input files, including netlist, control statement and library files, can be simulated by Eldo without any modification. In addition, Eldo also has a shell for the control interface. Through this shell, users can interrupt the ongoing simulation, exchange data, adjust simulation conditions or parameter settings, and interact with Eldo. This solves the problem that once the simulation runs, it can not carry out any control.
Sixth, function. In addition to providing almost all the functions of other spice, Eldo itself has its own unique functions. Eldo has comprehensive analysis function and can scan various parameters. Eldo can also perform RC reduction, save and continue simulation functions.
Seventh, support from process manufacturers. Circuit simulation is inseparable from the actual situation of the specific process line, and spice program must be supported by the process manufacturer. At present, most OEM manufacturers in the world have begun to support Eldo, such as TSMC, Taiwan union power, licensed semiconductor, St, etc. Users can also use their own defined models. In addition, because Eldo is fully compatible with HSPICE, even to the model, Eldo users can fully adopt the HSPICE model provided by the OEM.
3. Mach
SPICE simulation is characterized by high speed and slow speed. When doing analog circuit design, SPICE simulation can generally meet the requirements. However, when the circuit scale increases, especially after adding the digital circuit part of transistor level description, spice appears too slow. Under the same simulation conditions, the simulation time of spice does not even increase linearly with the increase of transistors, but increases exponentially. In this way, circuit simulation becomes the bottleneck of design, which is often encountered in the post simulation stage.
So mach came into being as fast spice. Based on Eldo, Mach rapidly improves the simulation speed by looking up the transistor model in the form of table. Compared with Eldo, Mach can improve the simulation speed by 10 ~ 1000 times. The cost of speed increase is, but the loss can be controlled within 3%. Mach's processing capacity is also very huge, reaching 20 million devices. Therefore, for some designs with less stringent requirements, Mach becomes necessary when fast verification is required, such as memory design.
ADMS is a mixed signal verification platform, which integrates the technologies of the above three tools. For the analog circuit, Eldo's simulation algorithm or Mach's fast simulation algorithm is adopted; For the digital part, the simulation algorithm of Modelsim is used. However, ADMS is not a simple combination of these tools. It has a single kernel engine.
Using ADMS for design, the traditional digital design process and analog design process are broken up and recombined. Designers can verify the circuit at any stage. Digital design and analog design form a whole through ADMS.
The released adms4.0 version adds SystemVerilog language and SystemC support, which makes ADMS support eight languages, namely VHDL, Verilog, spice, VHDL-AMS, Verilog AMS, SystemVerilog, SystemC and C, covering most of the current IC design languages. This makes the design method with ADMS flexible, but there is only one tool. There can be only one file input into ADMS. No matter whether the content is HDL, spice or C language, ADMS can read it, process it automatically and give the simulation results. For example, an IP described by HDL is introduced into the analog circuit, or an operational amplifier unit described by VHDL-AMS behavior level in the unit library attached to the tool. Various languages can be seamlessly combined.
ADMS provides flexible usage. It can be integrated into the circuit diagram editing tool da-ic of mentor graphics or into the schematics composer of cadence (Figure 3). In addition, it can be used alone. During application, the interface of ADMS is similar to the classic Modelsim, with simple operation. Its tree structure display makes the whole design clear at a glance. When in use, you only need to read in various input text files (digital structure can be used as the top level, or analog structure can be used as the top level), which can be simulated and debugged by ADMS.
The output file of ADMS can be viewed and calculated by a variety of waveform observation tools of other tools. However, ADMS comes with two powerful waveform processing tools xelga and ezwave, which can process digital and analog signals at the same time and carry out various operations and operations.
Eldo RF is developed on the basis of Eldo. New technologies are used for RF circuits. ADMS can also be extended to ADMS RF to become a tool for RF mixed signal SoC design.
ADMS comes with many behavior level description unit libraries called commlib, including more than 300 common basic units, such as ADC, DAC, PLL Σ-Δ、 OP, wait. Various libraries provide a large number of interface parameters for modification. These unit libraries can be called directly in the design to increase the simulation speed and facilitate the debugging of the circuit. Commlib also has a function of "behavior model calibration" (BMC). Through the verification of BMC and ADMS, the designed circuit diagram can be abstracted to the behavior level. During simulation, the simulation speed of behavior level is 1000 times faster than that of transistor level, which can abstract some circuits to behavior level, so as to increase the simulation speed and facilitate debugging. Abstract technology is more and more frequently used in large-scale circuit design.
Summary of this paper
ADMS is a real simulation / hybrid simulation tool, which can provide comprehensive language and design method support. At present, although there are few designers who are really doing mixed signal design in China, there is no doubt that they are gradually increasing. So, under what circumstances do we need to turn to mixed signal design? Perhaps it can be simply described as follows: when digital circuit design engineers using HDL simulators are faced with increasing analog part and analog circuit behavior, but suffer from insufficient model and simulation; When analog circuit design engineers using spice or fastspice are faced with increasing digital complexity and large scale, they suffer from too slow simulation speed. At these times, the use of mixed signal design can improve the design speed, efficiency and design level, and reduce the product cost“
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