"RF Identification (RFID) technology is a non-contact automatic identification technology that automatically identifies target objects through RF signals. Usually the RFID system is mainly composed of application software, radio frequency card, and card reader. [1] . With respect to the low frequency RFID system, the ultra-high frequency section (UHF) RFID system working on 860 MHz ~ 960 MHz has the advantages of reading distance, and the reading speed is fast. It is currently the hotspot of the development of RFID technology [2]. The design of the card reader is a key part of the RFID system design. There are a variety of design. FPGA [3] has the development of simple, static repeatable programming and dynamic online programming, has become a wide range of programmable integrated integrated circuits today. Many companies currently producing RFID products use their own standards, and several standards available for RF cards are ISO / IEC 11784, ISO / IEC 14443, ISO / IEC 15693 and ISO / IEC 18000. Among them, there are more applications. The three standards of ISO / IEC 14443, ISO / IEC 15693 and ISO / IEC 18000 [4]. This article is based on ISO / IEC 18000-6 Type B protocol design a card reader with a operating frequency of 915 MHz.
1 hardware design of card reader
The hardware of the card reader can be divided into three major modules: FPGA digital signal processing module, MCU, and human-machine interface module and RF transceiver module, which are shown in Figure 1. The FPGA digital signal processing module is used to implement the baseband data codes specified in the ISO / IEC 18000-6 Type B protocol, the MCU, and human-machine interface modules are used to implement the jump control of the instruction and some operational interfaces such as display of the data. The transceiver module is used to process the ultra-high frequency signal at the front end.
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1.1 FPGA Digital Signal Processing Module
The FPGA Digital Signal Processing Module contains clock division modules, FIFO, Manchester encoders, CRC generated checks, FM0 decoders, skewers and conversion circuits, and corresponding frame delivery controllers, which are shown in Figure 2.
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The internal workflow of the module is as follows:
(1) Send part
1 Data Communication Interface 8 Bit parallel to receive command data from the MCU, and the data buffers in FIFO.
2 Data do parallel to the serial conversion.
3 Under the control of the transmit controller, the serial data generates 16 BIT's CRC check value through the CRC module and attached to the original data.
4 According to the ISO / IEC 18000-6 TYPE B protocol, the above data is coded by Manchester.
5 lead the data encoded by Manchester to the shift register of a preset frame, and the data is started to activate the shift register, and then transfer the output data to the RF transceiver module.
(2) Receive part
1 Receive a frame baseband signal from the radio frequency transceiver module, detect the frame header with the shift register. If a frame header is detected, a signal that receives the frame header is sent to the receiving controller.
2 If the reception controller receives the signal of the frame header, the FM0 decoding is immediately started.
3 The decoded data is transmitted to the string / parallel conversion circuit, and the converted data is in the FIFO.
4 Simultaneous decoded data is also sent to the CRC module for verification. If the verification result is incorrect, the data stored in the FIFO is cleared, inform the MCU, the data error it receives; if the verification result is correct, the data in the FIFO Transfer to the MCU.
1.2 MCU and Human Interface Module
The MCU and human-machine interface modules consist of a peripheral circuit such as a C8051F020 microcontroller [5], composed of peripheral circuits such as the FPGA interface, the LCD, the PS / 2 keyboard, the UART interface, and the JTAG interface, as shown in Figure 3.
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The functionality implemented by the module is: (1) C8051f020 is responsible for coordination work in the entire card reader (including data communication with the computer); (2) Transferring configuration data to FPGA at startup, initializing FPGA; (3) The card command is transmitted to the FPGA during the card, and then start the receiving the FPGA signal by INT1 interrupt; (4) processing the received RF card information (card number, password, etc.); (5) implement binary tree anti-collision function; (6) Drive the LCD, display the prompt information of the system; (7) Extend a PS / 2 keyboard, you can enter data and commands; (8) Control the TR1000 chip, set an OOK emission mode or an ASK receiving method; (9) control the transmit power size; 10) Extend the EEPROM to store information about the read RF card.
1.3 radio frequency transceiver module
The development of the ultra-high frequency band RF transceiver module can generally adopt two options: one is to build a radio frequency circuit using a discrete component; the second is to adopt a wireless radio frequency transceiver module to achieve the modulation of the baseband signal [6]. Because the circuit commissioning of the method is more troubles, it will take a long development time, so this design takes a second solution.
ISO / IEC 18000-6 TYPE B protocol specifies ASK modulation of the reader to the RF card end for the modulation depth of 99%, that is, it can be approximated as an OOK modulation; while RF modulation mode of the radio frequency card to the card reader For reverse scattering modulation, its modulation is similar to the ASK modulation, so in the demodulation end can be demodulated in the ASK mode. The chip of the RF transceiver module uses RFM's TR1000 chip. The TR1000 is a single OOK / ASK universal radio frequency transceiver chip, suitable for high stable, small size, low power, low price short-range wireless data communication and wireless control applications.
2 software system design of card reader
Software design uses modular and structured programming ideas, and configures FPGA by single-chip in initialization. Taking into account the C language readability, portability and the actual situation of the MCU, this design uses C language to program C8051F020. The software system of the card reader can be roughly divided into: read and write card operations, arguing procedures, and serial communication programs.
2.1 Read and write card operation procedures
The read and write card operation procedure completes the baseband signal codes based on the ISO / IEC 18000-6 Type B protocol, and its programming flow chart is shown in Figure 4.
The specific work procedure is as follows: (1) Power-on reset, system initialization, including single-chip clock, port, LCD, timer initialization, configure FPGA and open interrupt. (2) Waiting for the command to receive the host or keyboard. (3) Judgment the instruction, if a multi-card operation is entered; if it is a single card operation, the card read, write card, value operation, and abort operation are performed. (4) If the operation is successful, the resulting data is passed back to the host computer while driving the LCD display operation success information; if the operation fails, the LCD display operation failed information.
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2.2 Anti-conflict procedure
When the card reader performs multiple card operations in the radio card, all RF cards within its antenna coverage will be activated and in recognition state, resulting in a plurality of radio frequency card read and write collisions. So resolve conflicts is the key to multi-card operation. The ISO / IEC 18000-6 Type B protocol specifies the anti-conflict mechanism, and its programming flow chart is shown in Figure 5. The principle of the anti-conflict mechanism is to implement binary tree search using randomly generated 0 and 1 signals, and set a success command to further improve the efficiency of the search, a binary tree anti-reperter algorithm [7]. The specific implementation process is: First, the RF card enters the working range of the card reader, from the off-field power-down state into the ready state. The card reader can participate in all or part of the radio frequency card in ready state within the reader in the reader work range through the groupseleet command and the groupunseleet command. Anti-conflict mechanism for this mode, the RF card should have the following two hardware circuits: an 8 bit counter and a 0,1 random number generator. When the RF card enters the identification status (ID state), the counter is cleared to 0, and some of which can be reset by receiving the groupunselect command to the ready state, other radio frequency cards in recognition state enters the process of conflict execution . The selected RF card begins the following cycle: (1) All RF cards in the identification state and the internal counter 0 will send its identification code; (2) If there is more than one RF card sends an identification code, the card reader will Detecting a conflict and send a fail command; (3) All RF cards that receive the fail command and the internal counter does not equal 0 will add the counter's counter plus 1; all the radio frequency cards that receive the FAIL command or equal to 0 (ie just send The radio frequency card of the admittance will produce a random number of 1 or 0. If 1 is selected, the RF card will add its own counter 1; if 0, the RF card will hold the counter 0 and send their identification code again. 4 possible situations occur during the next process; (4) case 1: If there is more than one radio frequency card transmission, repeat step (2); (5) case 2: If all of the RF card is randomly selected 1, the card reader will not receive a response. At this time, the card reader will send the success, all the RF card counter minus 1, then the counter is equal to 0 RF card to start, and then repeat step (2); (6) If only one RF card is sent and its identification code is received correctly, the card reader will send the DataRead command containing the identification code. When the RF card will receive the command correctly, it will enter the data exchange status and start sending it. The data. Thereafter, the card reader will send the success command to reduce the counter of the RF card in the identified state; (7) case 3: If only one radio frequency card is equal to 0 and returns a response, repeat step (5) card reader SUCCESS command or repeating step (6) Send a DataRead command; if there is more than one RF card returns a response, repeat step (2); (8) case 4: If only one RF card returns a response, and its identification code is not correct Receive, the card reader will send a resend command. If the identification code is received correctly, repeat step (5). If the identification code is repeated several times (this number can be set based on the desired error processing criteria), it is assumed that more than one RF card is in response, repeats step (2).
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After the above anti-collision process, the RF card in the radio frequency field will be identified one by one and perform data exchange.
2.3 Serial Communication Program
The system uses the PC as a host computer, and the card reader is used as the lower computer. Communication between the host machine and the lower machine is employed based on RS-232-C serial communication. RS-232-C is a serial communication bus standard, an interface criterion between data terminal devices (DTE) and data communication devices (DCE), equipment produced by different manufacturers, as long as they have RS-232-C standards Interface, you don't need any conversion circuit, you can connect together.
The serial communication program is a control program for MCU and PC communication. The sender is designed by the query, that is, the data to be sent first in the buffer, and then querying the serial transmission interrupt flag is free, if free, send the next data.
The receiving program is designed by an interrupt, i.e., when the PC must send data to the MCU, actively apply to the MCU to apply to the MCU, the received interrupt flag is valid, then the PC transmits data to the MCU.
3 verification plan
3.1 Establishment of Verification Platform
In order to verify that the designed card reader can complete the expected function, the corresponding verification platform [8] is designed [8]. The verification platform consists of three parts: data decoding channel, data coding channel, and instruction analyzer. The data decoding channel is decoded to decode the data frame transmitted by the card reader. The original data of the instruction is extracted; the instruction analyzer is judged by the received command data, and the corresponding data is returned and transmitted to the data coding channel; the data coding channel Then, the transmitted data is encoded, and then sent to the card reader.
The platform is built with Verilog HDL hardware language. The EP1C6Q240C8 chip in Altera Cyclone series is used as the target device. It uses Quartus II to perform comprehensive verification. The structural block diagram and circuit schematic are shown in Fig. 6, and Fig. 7, respectively.
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3.2 Analysis of Test Results
(1) Timing analysis
Some parameters of timing analysis can be obtained by running quartusii 7.1, and some parameters of timing analysis can be obtained: TSU (input establishment time), TCO (clock to output delay), TH (holding time) is 3.530 ns, 13.174 ns, 0.751 ns . The base frequency clock CLK can reach 89.06 MHz, while the fundamental frequency clock specified by the ISO / IEC 18000-6 Type B protocol is 40 kHz. From the analysis of the timing results of the system, it is fully compliant with the protocol requirements. The specific timing analysis results are shown in Figure 8.
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(2) Function analysis
Function analysis takes the group_select_lt command as an example. The group_select_lt command is the group selection command in the multi-card operation. The RF card is connected to this command, and the data of the address is specified in the card is compared to the data provided in the frame. If the internal data is small, return to the 64 bit serial number of the RF card, otherwise it will not be any response. The command number of the group_select_lt command is 03, the address is set to 0F, and the mask is set to FF, and the 64 bit data is set to f, so the command data transmitted to the FPGA from the MCU is 03_0F_FFFFFFFFFFFFFFFFFFFFF. After the original data is processed by the FPGA digital signal processing module, a frame baseband data signal is formed. The verification platform decodes the data frame sent by the card reader, then determines the instruction and returns the 64 bit serial number of the RF card, and is transmitted to the card reader after encoding. After receiving this frame, the card reader is decoded, and the CRC check is performed. If it is not wrong, the decoded data is transferred to the MCU.
The group_select_lt command simulation waveform is shown in Figure 9, the experiment proves the ISO / IEC 18000-6 Type B protocol.
With the establishment of RFID-related international standards (such as ISO / IEC 18000) RFID has become an international topic. In many RFID operating frequency bands, the RFID technology prospect of the UHF band is optimistic.Also become a hot spot in the field of RFID technology.
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Source: Wiku Electronic Market Network
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