With the increasingly mature software radio theory, software radio technology is increasingly applied to military or civil communication systems. Among them, digital downconverting techniques (DDC) are one of the technologies in software radios. Digital down-frequency operation After the analog front-end input analog signal is converted by analog to digital signal processing, it is primarily used to achieve the intermediate frequency signal spectrum to zero, and then extract the signal to make the sampling rate. The processing rate required to change to the backend digital signal processing unit.
Currently, as A / D transformation is increasingly developing RF front end, high-speed sampling rates have brought more and more pressure on subsequent digital signal processing and coordination of the entire system. In order to solve the problem of difficult to match between high-speed sampling between the high-speed sampling power, a multi-phase filtering-based digital lower frequency conversion structure is designed, and the parallel structure of multi-phase filtering inverter is designed to numbers. In the inverter, in the subsequent mixing module, in a subsequent mixing module is also implemented, real-time processing speed is improved. From the principle analysis and the FPGA board verification, the design is verified, which proves that the data rate after the multi-phase filtering digital down-converter processing can meet the requirements of the existing DSP device processing capabilities.
1 Wideband orthogonal digital lower frequency conversion technology based on multi-phase filtering
1.1 band-through sample theorem
With a pass sample, set a frequency band signal x (t), which is limited to (FL, FH), if the sampling frequency satisfies FS:
In the formula, N-be taken to meet the positive integers of FS ≥ 2 (FH-FL) = 2b, then the signal sampling value X (NTS) obtained by equally spaced sampling with FS can accurately determine the original signal x (t). Obviously, when FL = 0 and fH = B, select n = 0, formula (1) is a NYQUIST low pass sampling theorem, which is a special case of tape sampling.
In the actual digital receiver, the bandwidth B of the signal is generally smaller than the frequency of the signal. If it is still designed according to the Nyquist sampling rate, the sampling frequency of the ADC will be high, so that it is difficult to implement, or the speed of the post-processing is also satisfied. I can't ask. Therefore, it is natural to consider the band-through-calibration theorem with no loss information. The intermediate frequency signal input by the digital receiver is a band pass signal, and the receiver digitization is typically performed in the intermediate frequency, so various electronic equipment can be used to sample the analog signals using the tape sample theorem.
1.2 orthogonal digital down frequency
The digital mixed orthogonal transform is actually the first to form a digital sequence X (N) after the sample signal X (t) is formed by the sampler, and then multiplied by 2 orthogonal sequences COS (ω0n) and SIN (ω0n). , Reappeared by digital low pass filter. The implementation block diagram is shown in Figure 1.
Figure 1 orthogonal digital downconversion structure diagram
After the orthogonal figures are quarantined, the sampling rate can be reduced, so the low-pass filter is often taken.
Orthogonal digital downfremount can realize the balance of IQ branch, in order to achieve strict orthogonality, usually need to perform IQ equalization processing, ignore frequency conversion methods to be widely used in frequency modulation and phase modulation applications.
1.3 Extractor multi-phase filtering
Assuming that the impact response of the FIR digital filter is h (n), the definition of its Z transform is expanded and rewritten as:
After the merger, it can be written as:
The formula (4) is a multi-phase filter structure of digital filter H (Z), and the equivalent relationship of the extractor is used, and the multi-phase filter structure after equivalent optimization is shown in FIG.
The substance of multi-phase filtering can be seen as a relationship of phase average to decompose the transfer function H (z) of the digital filter into a plurality of different phases, forming a plurality of branches, and filtering on each branch. The purpose of this is to filter Filtering of H (Z) of the original order with less steps in its branch. The meaning of this is that the engineering is easy to implement, and can efficiently perform real-time signal processing.
2 FPGA implementation design
2.1 system design
After the signal received by the antenna is processed by the radio frequency front end, the signal mixing filter is reduced to the intermediate frequency of 1000 MHz, with a bandwidth of 200 MHz. Since the bandwidth of the signal is 200MHz, it is possible to consider the tape sampling, and the N value in the formula 1 is 2, and the sample rate is 800 MHz. The digital processing section requires the signal analysis of any 100 MHz bandwidth signal in 200 MHz bandwidth to zero, transmitted to the DSP.
The data transmitted by the sampler is two DDR forms. First, the DDR operation is performed on the sampled data stream that receives the FPGA, turns a 4-way 200MHz data stream.
2.2 variable frequency
The data stream of the high sampling rate is quite consumed in the FPGA, so for the FPGA processing of the broadband signal, it will be very meaningful if it can reduce the amount of operation.
Considering that a signal with an 800 MHz sample rate is a medium frequency of 1000 MHz, it is equivalent to the signal digital frequency of 200 MHz. If the intermediate frequency of this signal is first moved to zero, the design bandwidth of the digital low-pass filter is half the signal bandwidth, so that the sampling rate can be reduced by half again and then processed.
For 800MHz sampling rate to generate a 200MHz downconverted local oscillator signal, just 4 data points in one cycle, can use a DDS sequence of a special phase relationship, the cosine sequence value is taken 1, 0, -1 and 0, respectively The sinusoidal sequence value takes 0, 1, 0 and -1, then this down frequency is very simple, and for the branch of 0, it will not need to be calculated; for the branch of 1, quite The data delay is taken; for the branch of -1, it is equivalent to the operation of 1 after the data is reversed. The lower frequency conversion processing of this special phase relationship has hardly consumes internal resources of the FPGA, and does not introduce spurious scathers generated after the frequency conversion.
2.3 multi-phase filtering FPGA implementation
Considering the resource consumption and system stability factors of the larger circuit, the decomposition 4 200MHz data is subsequently processed, and it is actually half of the IQ data after frequency conversion. Zero, these branch subsequent filtering will not be required, saving half of resources.
The 8-way data stream is X0, X1, X2, X3, X4, X5, X6, and X7, decompose the filter transfer function, and sub-filter after eight-phase decomposition is H0, H1, H2, H3, H4, respectively. , H5, H6 and H7, the relationship expression between the output signal and the input signal can be obtained by decomposition:
Because the multi-phase filtering signal spectrum width is reduced by half, the data can be done twice the data, so the data selects half of the multiphase sub-data branch, and saves half of the resources. Here, the output Y1, Y3, Y5, Y7 of the even branch is selected and the even value of the variable frequency vibration DDS cosine sequence is 0, and the odd value of the sinusoidal sequence is 0, and the multiphase expressions of the same phase branch are generated. For:
The multiphase expression of the orthogonal branch is:
2.4 secondary frequency conversion
If the signal to be processed is 100 MHz bandwidth of the 200MHz bandwidth center, the signal after the frequency conversion and multi-phase filtering can meet the requirements. If the bandwidth of the subsequent processing signal contains the 50MHz signals in both sides, the first The digital frequency conversion operation of the second level can meet the requirements of the system, and the data stream after multi-phase filter is 4-way 100MHz orthogonal data. Here, the output representation of the secondary frequency conversion DDS local oscillator is also a 4-way parallel orthogonal carrier data, and only the sub-data stream of 4 branches can be completed with the double-carrier of 4 branches. During the implementation of the FPGA, four phases of DDS intrinsic nuclei were separately described, and then the same phase accumulated words and different initial phase values were completed, and the configuration of the multi-phase reset IP core was completed.
3 Test Simulation and Engineering Verification
The FPGA program for this system has developed Xilinx's ISE12.4 hardware development tools. FPGA Select V6SX315T chip in the V6 series. The system is implemented in VHDL language programming.
The system sampling rate is 800MHz, and the analog signal of the input AD sampler is 10,000 MHz and the bandwidth is 200MHz. The prototype low-pass filter design uses MATLAB aided design, selects filter design tool, and the filter normalized belt is 0.25, the strip is 0.42, the order is 48th order, and the band is suppressed to 60 dB. The function is verified using a mono signal. The signal frequency is 960 MHz. After the frequency conversion and the frequency signal is 1160 MHz, the difference frequency signal is 760 MHz, and the corresponding digital frequency is 360 MHz and 40 MHz, respectively, where the difference frequency 40MHz is the preserved signal, as shown in FIG. With the frequency of 60 dB of filter suppression, the spectrum is moved upward by multiphase DDS, and the frequency of the preserved signal is 60 MHz, and the result is shown in FIG.
Figure 3 signal spectrum after two frequency conversion
If a conventional multi-phase filtering structure is used to achieve a broadband digital down-frequency structure, 8 filter branches must be calculated, then the multiplier will consume more than 768 DSP48E. 384 DSP48Es consume 384 DSP48E in this paper, the internal resources of the FPGA can save a lot.
4 Conclusion
A method of implementing a broadband digital orthogonation inverter based on FPGA design is proved that the FPGA circuit is stable and reliable by the actual board test. Introduced the principle of tongs the sampled orientation and orthogonal digitalization, and theoretically derive the mathematical model of the multi-phase filtering of the extractor, combined with the implementation characteristics of the FPGA, use two frequency conversion and multi-phase filtering methods, the broadband spectrum is completed Movement, using parallel processing to improve processing real-time, reducing the amount of computation by multi-phase filtering, saving a large number of FPGA resources, reducing the power consumption of board card, strong engineering can be achieved .
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