"1. AHB system bus is divided into apb1 (36MHz) and apb2 (72mhz), where 2 > 1 means that apb2 is connected to high-speed equipment
2. Stm32f10x. H is equivalent to reg52. H (there are basic bit operation definitions), and the other is stm32f10x_ Conf.h specifically controls the configuration of peripheral devices, that is, the role of switch header files
3. HSE OSC (high speed external oscillator) high-speed external crystal oscillator, generally 8MHz, HSI RC (high speed internal RC) high-speed internal RC, 8MHz
4. LSE OSC (low speed external oscillator) low-speed external crystal oscillator is generally 32.768KHz, and LSI RC (low speed internal RC) low-speed internal crystal oscillator is about 40KHz. It provides watchdog clock and clock source of Automatic wake-up unit
5. Sysclk clock source has three sources: HSI RC, HSE OSC and PLL
6. MCO [2:0] can provide 4 different clock synchronization signals, PA8
7. GPIO port seems to have two diodes in reverse series as clamping diodes
8. The bus matrix arbitrates the system bus and DMA using the rotation algorithm
9. Icode bus, dcode bus, system bus, DMA bus, bus matrix, AHB / APB Bridge
10. Register RCC must be set before using a peripheral_ Ahbenr to turn on the clock of the peripheral
11. Data bytes are stored in memory in the form of small end storage
12. The memory map is divided into 8 blocks, each of which is 512MB
13. One page of flash is 1K (small capacity and medium capacity), and the large capacity is 2K
14. The system memory is the factory configuration of ST company and locked, which cannot be edited by the user. It is used to reprogram the flash area. Therefore, we must select boot1 = 0 to burn the program, so that we can burn flash through the embedded bootstrap program, such as interrupt vector table and code
15. The core voltage of STM32 is 1.8V
16. There are three kinds of STM32 reset: system reset, power on reset and backup area reset. System reset except RCC_ Except that the reset flag in CSR and the value in BKP are not reset, all other registers are reset. Trigger mode, such as external reset, watchdog reset, software reset, etc; Power reset due to power on / power off reset of external power supply or standby mode return. Reset all except the register value in BKP does not move; The trigger source of backup area reset is software reset or when Vdd and Vbat are all powered down
18. 68 maskable interrupt channels, 16 programmable priorities, 16 kernel interrupts, 68 + 16 = 84 interrupts in total. There are only 60 interrupts in 103 series and 68 interrupts in 107 series
19. The system starts from 0x00000004 and 0x000 0000 is reserved
20. (nested vector interrupt controller) NVIC nested vector interrupt controller is divided into two types: preemptive priority (can be nested) and interrupt priority (sub priority, can not be nested). Both priorities are determined by 4-bit binary bits. There are 16 situations:
21. Interrupts with preemptive priority No. 0 can interrupt any interrupt with preemptive priority other than No. 0; Interrupts with preemptive priority No. 1 can interrupt any interrupt with preemptive priority No. 2, 3 and 4; Constitute interrupt nesting. If the preemptive priority of two interrupts is the same, the one who appears first will respond first, which does not constitute nesting. If they appear together (or hang there and wait), it depends on whose sub priority is higher. If the sub priority is the same, it depends on their interrupt vector position. It turns out that the position of the interrupt vector is the final determinant
22. After power on initialization, airc is initialized to 0, which is 16 preemptive priorities. However, due to the interruption of all external channels, the priority control word pri_ N is 0, so the preemptive priority is the same. At this time, it cannot be nested
23. There are definitions of Iser [2] (interrupt set enable registers), ICER [2] (interrupt clear enable registers), ISPR [2] (interrupt set pending registers), ICPR [2] (interrupt clear pending registers), IABR [2] (active bit registers) and IPR [15] (interrupt priority registers) in NVI. Iser and ICER are interrupt enable and interrupt disable registers respectively, which are written with 1 enable / disable interrupt. Why write 1? Why not use one register and two registers to represent the interrupt enable / disable state? Due to the complexity of hardware, writing 0 may cause the state of other bits to change, so it is reasonable to use 1 to indicate on or off
24. The interrupt sign bit needs to be cleared manually
25. General steps for configuring peripheral devices: 1. Turn on the port clock. 2. Define the initialization structure and initialize. 3. Call
26. Parity check of serial port: if it is parity check, USART_ InitStructure.USART_ WordLength= USART_ WordLength_ 9b; The length of this data must be set to 9 bits!
27. The rule group of ADC can customize the conversion channel order and the number of conversion channels. In practical applications, it is sometimes desirable to have some special channels with high priority. When the rule group is converted, it is necessary to forcibly interrupt to convert another channel. Such a group of channels is called injection group
28. Timer output comparison mode: timing (freezing, doing nothing, normal timing), active (ocxref output high level is valid), inactive (ocxref output low level), toggle (flip level after successful comparison)
29. The timer of STM32 starts counting from 0, meets some conditions, gives flag bits (such as matching success, time update, overflow, etc.), and then starts counting from 0. This is different from 51
30. OCX = ocxref + polarity
31. Automatic loading register and shadow register: the former is equivalent to the overflow setting value in 51. The shadow register, as its name implies, is another copy of the register. What actually works is the shadow register, while what the programmer manipulates is the automatic loading register. If the appe bit is enabled, it indicates that the value of the auto load register will not be written to the new value until the next update event occurs. Otherwise, the value written to the autoload register is immediately updated to the shadow register.
32、RCC_ PCLK1Config(RCC_ HCLK_ Div4); 4 frequency division of pclk1 gives the timer reference clock
33. Timer configuration: RCC, NVIC, GPIO (OC output or PWM), timx
34. The general timer can output 4 different PWM channels. The advanced timer can output 4 different PWM channels. In addition, it can also output 3 complementary PWM signals (driving three-phase motor), a total of 7 channels. In this way, STM32 can generate 30 channels of PWM = 7 * 2 + 4 * 4
35. Flip the output signal when the value of the counter is equal to the output comparison register
36. The advanced timer clock source is hung on apb2, while the general timer is hung on apb1. AHB (72mhz) → apb1 frequency divider (default 2) → apb1 clock signal (36MHz) → frequency multiplier (* 2x) → general timer clock signal (72mhz). If apb1 has no frequency division, the clock signal frequency of the general timer is directly equal to the clock frequency of apb1 without the above frequency multiplier * 2 process. TIM_ Setautoreload() is used to change the frequency of PWM, Tim_ Setcompare1() is used to change the duty cycle
37. Generally, the starting torque of brush motor is larger, while the starting torque of brushless motor is small and the running torque is large. The brush motor adopts brush mechanical current commutation, while the brushless motor measures the current of the rotor through the hall sensor to judge the moving position and direction of the motor and return it to the control circuit
38. Dead zone is necessary because it involves the short circuit of the circuit. The thyristor needs dead time to completely shut off the line during commutation
39. The braking function is used to automatically give emergency braking to the external motor when there is a problem in the control circuit, and continuously give a fixed duty cycle on the PWM（ Three phase drive?)
40. PWM mode is best used for PWM output. The phase of other comparison output modes will change slowly and inaccurate
41. The reading and writing of flash needs to be unlocked first and then locked. Flash is easy to write 0, but difficult to write 1
42. There are two ways to download the program. One is ICP (online programming), which is applicable to the burning program under JTAG or SWD protocol. The other is called IAP (in application programming), which is suitable for downloading many interfaces (USB, serial port, can) to the memory. IAP allows to re burn flash when the program is running
43. Flash is divided into main memory (where the user's program code is placed) and information block (startup code). In addition, there is a part called system memory. This block is inoperable for users and solidified after production by ST company. It is the power on bootstrap program of the system
44. Flash must not be read when writing. If there is a read operation, the bus will be locked
45. When operating flash, his must be turned on
46. STM32 has two kinds of watchdog (iwdg independent watchdog "independent clock" and wwdg window watchdog "from apb1 frequency division")
47. The maximum frequency of SPI is 36MHz (fpclk / 2)
48. When TIM1 and tim8 advanced timers output PWM, they need to configure the main output function (ctrlpwmoutputs) to output PWM. Other general timers do not need this configuration. However, tim6 and tim7 have no PWM output function
49. Code is the program code part. Ro data represents the constants defined by the program (such as const temp, etc.); RW data represents initialized global variables, Zi data represents uninitialized global variables, and variables initialized to 0 code, RO data, RW data.............. flash, RW data, zidata.............. RW data is copied from flash to ram during ram initialization
50. Stm32f103zet6 has 144 pins (z is 144), of which 112 are available IO ports (7x16 = 112, ABCDEFG port)
51. Arm only produces core standards, not chips. Companies such as st and Ti buy cores from arm, and then add their own bus structure, peripherals, memory, always reset and I / O to form their own chips. The structure of Cortex-M3 chip is shown in the figure below
52. CMSIS standard is used to exchange information at the upper user layer and the lower hardware layer. Of course, this architecture can be defined by itself, but there will be no standard. Therefore, it is mandatory to use cmsisi standard to design chips. Generally speaking, the function name CMSIS of system initialization is defined as systeminit(), GPIO_ Resetbits(), etc
53. Port multiplexing and port remapping are two concepts: the former can only enable its corresponding port and corresponding function clock. The latter needs to turn on the Afio clock, and then remap the GPIO port_ PinRemapConfig()
54. The download program can only use serial port 1. Pay attention to it in hardware design!
55. The J-TAG debugging frequency is generally set to 2MHz, while the SWD debugging frequency can be set to 10MHz
56. Systick interrupt can be implemented in two ways: cyclic waiting and interrupt method. Circular waiting is recommended. The interrupt method may cause problems and occupy resources
57. Some I / O pins are 5V compatible. The maximum driving current and filling current of a single I / O are 25mA. The current of the whole chip is 150mA
58. Keil supports bit segment operation. You can use the bit segment knowledge in C language to define the bit segment structure, and then perform separate bit operations on separate registers
59. Setting of internal pull-up resistance: if the other end of the external key is grounded, it needs to be set as a pull-up resistance（ The reason is that when the key is not pressed, the input is high due to pull-up; When pressed, the input is low due to external ground.) Similarly, if the other end of the external key is connected to the high level, it needs to be set as the pull-down resistance
60. The difference between serial port interrupt TXE and TC: in fact, it is obvious that one is the send register empty flag and the other is the send completion flag. Because the serial port needs to shift the data in the transmission register to the shift register (shadow register) before serial transmission. Therefore, when the transmission register DR is empty, it means that data may be being sent out, and the data may not be sent yet. However, the completion of transmission is different. It is the flag bit set after the shift register shifts all the data this time (that is, the stop bit after transmission). In this way, TXE allows the program to have more time to fill in the TDR register to ensure the uninterrupted data flow. TC can let the program know the exact time when the sending ends, which is helpful for the program to control the timing of external data flow
61. As the name suggests, the window watchdog has a window whose abscissa is time, which means to refresh the register within the specified time range, otherwise the MCU will reset. The upper limit of the window is set by someone w [6:0], and the offline setting is 0x40twwdg = (4096) × 2^WDGTB ×( T[5:0]+1)) /Fpclk1； Twwdg is super
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