"Keywords:
Mg3500, codec, HD, system on chip
1 Introduction
According to the requirements of consumer and industrial H.264 encoder, even in the case of limited storage capacity or limited broadband, it must provide the best video quality. Therefore, this paper presents an on-chip system mg3500 application design supporting H.264 HD encoder, which is very general for the related applications of HD video codec.
2 mg3500 SOC introduction
Mg3500 SOC (system on chip) is an H.264 high-definition codec on-chip system launched by mobilygen company. It integrates embedded ARM9 processor, NAND / NOR flash memory, SD / SDIO / MMC / ce-ata interface, MAC and USB2.0 OTG port of 10 / 100 / Gigabit Ethernet, AES / Sha encryption algorithm based on reliable internet, UART, JTAG, serial control and general I / O. The 240 MHz ARM9 processor includes DSP extensions and 16 KB instruction cache, data cache and temporary storage.
The mg3500 SOC supports the basic level, main level and high image quality up to level 4.1 of H.264. The macro module adaptive field / frame (MBAFF) coding in the main grade and high image quality allows the highest quality per bit of interlaced material. It also supports integrated circuit devices (ides) and compact flash.
2.1 main characteristics of mg3500 SOC
(1) HD H.264 codec dual stream HD / SD H.264 codec supports the basic level, main level and high image quality of H.264, and the H.264 codec resolution is up to 1920 × 1080 I, programmable resolution and frame rate, multi stream SD codec, video bit rate range: 64 kb / S ~ 62.5 MB / s, macro module adaptive field / frame (MBAFF).
(2) MPEG-2 decoder HD / SD decoder converts HD MPEG-2 code stream into H.264 format in real time, and multi stream SD MPEG-2 decoding.
(3) JPEG / MJPEG codec, JPEG codec, HD / SD MJPEG, support exchangeable image file format (EXIF).
(4) Audio codec high fidelity dual channel aac-lc codec, MP2 format codec, MP1 and MP3 format decoder, Dolby Digital 5.1 channel decoding, G.711 codec, adjustable bit rate and sampling frequency, support codec expansion, 1-channel Sony / Philips home digital audio output interface (s / PDIF) or 2-channel I2S Audio I / O port.
(5) The video input processor (VIP) has adjustable video direct input, two ITU-R bt.1120 parallel interfaces, four itu.r BT.656 parallel interfaces, and two advanced video input processors, which support digital image stabilization and smooth digital zoom.
(6) Video output processor (VOP) can support HD / SD output of ITU-R bt.1120 or ITU-R BT.656, multi stream decoding, picture in picture and multi-channel mixed video output, 18 bit or 8-bit RGB format LCD interface, high-quality video compression output, 2 bands α Mix and cursor overlay layers to generate selectable external synchronization signals.
(7) Built in arm926-ej processor, 240 MHz general-purpose processor, 16 KB data cache memory, 16 KB instruction cache memory and 16 KB temporary memory.
(8) System connectivity: 1 10 / 100 / Gigabit Ethernet MAC, 1 USB2.0 OTG port, high-speed bitstream I / O port, AES / Sha encryption.
(9) The peripheral interface supports SD / SDIO / MMC / ce-ata interface, IDE and compact flash
(10) Universal interface, 2 SPI or two bus serial communication interfaces, 3 UART interfaces, 3 pulse width regulators, 8-Channel special GPIO. It can be extended to 72 channel GPIO.
(11) The system core voltage is 1.0 V ± 10%, the SDRAM voltage is 1.8 V ± 10%, and the I / O port voltage is 1.8 V, 2.5 V, 3.3 V ± 10%. The single crystal driven audio / video PLL.
(12) Power consumption (mg3500 + SDRAM) H.264 HD 30fps + AAC coding 750 MW.
2.2 mg3500 SOC interface
Figure 1 shows the functional structure block diagram of mg3500 SOC. There are 2 video input processors (VIP), 1 video output processor (VOP), 1 video multimedia engine (MME) and 1 audio multimedia engine in the mg3500 SOC. The two same VIPs can perform high-quality video scaling, chroma and gamma adjustment, filtering and video extraction and analysis, and can process two independent video inputs with a maximum resolution of 1920 × 1 080 i； VOP supports high-quality video compression output, 2 graphics memory areas and 1 hardware cursor, supports chroma and gamma adjustment, and can output full TV signals. Each graphics memory area is 1 ~ 32 bits: Video Mme is a proprietary reduced instruction set computer (RISC), which is used for single cycle context switching and low-power optimization, and controls VIP, VOP and video kernel.
2.2.1 video interface
Two 8-bit video input interfaces support independent ITU-R BT.656 input, and each video input supports independent clock and synchronization signal. Support standard definition input, set the clock frequency above 100 MHz, and also support non-standard video signals including 8-bit video signals from HD sensors. Two 8-bit video input interfaces can also be combined into one 16 bit ITU-R BT 1120 HD input interface. The operating modes supported by the mg3500 SOC are listed in Table 1.
2.2.2 audio interface
The audio multimedia engine of mg3500 SOC can make all audio codecs effective. The audio interface includes 2 I2S inputs and 3 I2S outputs. One I2S input is connected to the audio clock, and the other I2S input and three I2S outputs are connected to the other clock. One of the audio output ports can also be used to generate s / PDIF compatible audio.
2.2.3 Ethernet port, USB interface and SD / MMC interface
The Ethernet media access controller (MAC) of mg3500 SOC supports 10 / 100 / Gigabit Ethernet through a media independent interface (MII), reduced independent media interface (RMII) or Gigabit media independent interface (gmii). Mg3500soc can also be directly connected to the Ethernet switch supporting revmii interface. The USB interface supports high-speed USB 2.0 OTG and can be the master device or slave device. The SD / MMC interface is used to support SD / SDIO / MMC / ce-ata devices. The clock frequency of this 4-bit interface can reach 50 MHz.
2.2.4 host interface
The mg3500 SOC can operate in both master and slave modes. When the mg3500 SOC works in the main mode, the signal line of the host interface is used to connect nor flash, NAND flash, compact flash, IDE and other external devices. Serial port and other I / O ports. The mg3500 SOC includes a plurality of asynchronous transceiver ports (UART) for communication, a pulse width regulator (PWM) for control, a two bus serial communication interface (TWI) for peripheral control and a serial peripheral port (SPI). The eight dedicated general purpose I / O ports (gpios) of the mg3500 SOC and the other 64 multiplexed gpios can be used for system control. These multiplexed GPIO pins have many different uses. The GPIO function can be used only when the main function of this pin is not used.
3 typical applications
The typical application of mg3500 is vehicle DVR, because it has the highest quality high-definition (hd) H.264 encoding / decoding for processing multiple standard definition (SD) data streams, and also provides extensive network support for transmitting secure video data streams over IP networks; Typically, an en vie codec requires only 500MW power consumption for 108li coding, which is only one tenth of that of the DSP based solution. Figure 2 is the functional block diagram of the main board module of the on-board DVR, including linear power supply circuit, CPU, SDRAM, reset circuit, flash memory module and FPGA logic circuit.
Transform tw2864 non-standard I2S into standard I2S, provide one I2S as network intercom, combine data stream with audio input and input to mg3500, audio and video input and output, audio and video coding adopts tw2864, audio decoding adopts tw2864, video decoding adopts ADV7393, serial port expansion circuit, peripheral RS232, RS422, USB, one Ethernet, switching value signal detection and output control circuit, Alarm input and output, working status indication. Sb is extended through USB hub, and equipment status indication, alarm input and output, switching value detection and can are completed by ARM7.
On board DVR converts four analog vehicle audio and video signals into digital signals in BT.656 format through special a / D converter. The processor compresses the data into H.264 format data and stores it in hard disk. It has fast and convenient query and playback mode, high-speed USB2.0 interface and broadband network interface to facilitate data backup. At the same time, combined with the particularity of the vehicle industry, it can expand other functions such as film and television broadcasting, automobile black box and so on.
The hardware function block diagram of on-board DVR is composed of power board module, audio and video coding module, audio and video decoding module, data storage module, external interface module, I / O acquisition module, etc.
The power board module provides reliable and stable power supply for the system and provides overvoltage and overcurrent protection; Common mode and differential mode interference filtering; Output voltage signals of 12 V and 5 v.
The audio and video coding module is the focus of the system design. Tw2864 realizes 4-channel audio and 4-channel video coding. Due to the limitation of the number of mg3500 video capture ports, 4-channel 27 MHz BT.656 format video output from tw2864 flows through the ddriiram cache connected to FPGA, and then becomes 2-channel 54 MHz video stream input to the mg3500 video capture port for processing by mg3500. Tw2864 converts the four input analog audio signals into digital signals, and then inputs them to mg3500 through one I2S port for processing.
The audio and video decoding module realizes the functions of real-time image preview and image return visit. The video decoder converts the digital signal output by the CPU into an analog video signal that can be transmitted remotely.
The data storage module mainly includes two parts: hard disk and SD card to realize the local storage of audio and video data. Important, such as alarm data, realize the dual backup of hard disk and SD card. At the same time, SD card can also be used for program update, log storage, data reading and other functions.
The external interface module mainly includes usb2.0highspeed, Ethernet, RS485, RS232, etc. USB realizes data transfer, mouse and other USB devices; Ethernet interface realizes network backup of data, network parameter setting, video network preview and other functions; RS485 is used for external PTZ; The RS232 interface is externally connected with GPRS / CDMA modules, and can also be connected with other RS232 devices. The I / O acquisition control module realizes the collection of alarm quantity, the output of external alarm quantity, the collection of vehicle status, and the indication of equipment status.
Problems needing attention: the speed of USB is the bottleneck of this part. Mobilygen does not support users to expand the USB port with expansion devices. Therefore, USB hub is used. The can interface device adopts arm7lpc2109 with can interface. For example, LPC2119 can be used for two channels. Because the SPI port is occupied and the number of gpios of mg3500 is not enough, the alarm, vehicle status acquisition and can are completed by one piece of ARM7, Mg3500 IDE interface only supports 128 G hard disk and can only use USB to SATA bridge.
4 Conclusion
The mg3500 SOC launched by mobilygen company can handle the highest quality HD H.264 codec of multiple standard definition data streams. At the same time, it also provides extensive network support for transmitting secure video data streams over IP networks, and also includes an MPEG-2 decoder and a JPEG codec supporting motion JPEG format. At the same time, some H.264 codecs for consumer and industrial applications. It is required to provide the best video quality even in the case of limited storage capacity or limited bandwidth. Therefore, mg3500soc will have a wide application prospect in these application fields“
Our other product:
