It is reported that the TSMC board has recently adopted the decision of the construction of the advanced seal testing plant in Zhunan, and is located in Miaoli County Zhunan Science Park. The beta plant is expected to have a total investment of approximately RMB 71.62 billion, which is planned to operate in the first phase of the year next year. In addition to Tajimad, SMIC is also placed with long technology joints, layout wafer level packages. How to the TSMC layout has a moving machine? The wafer large factory continues to add a package industry, which affects what influences on the competition between the industry chain downstream?
Leading crystal round package
TSMC is more than just the leader of the global wafer foundry, but also the leader of the wafer level package. After ten years of layout, TSMC has formed a wafer-level system integration platform including COWOS (Substrate wafer packages), Info (integrated fan-out package), SOIC (system integration single wafer package).
TSMC packaging technology focuses on wafer level packages, compared with the general package, the largest feature of wafer level packages is "first sealing". According to the application material, the wafer level package is encapsulated on the wafer, rather than cutting the wafer into a single chip and then packaged. This solution enables greater bandwidth, higher speed, higher reliability, and lower power consumption.
COWOS is the first batch of wafer-stage package products launched by TSMC, which was first applied to 28 nm FPGA packages in 2012. Cowos can achieve more dense chip stacks, suitable for high-performance computing markets with high connection density and large packaging dimensions. With the outbreak of AI chips, COWOS has become a powerful weapon for TSMC attracting high performance computing customers, and its derived version is applied to Ying Weida Pascal, Volta Series, AMD VEGA, Intel Spring Crest and other chip products.
Info packaging, TSME is strateting in the competition with Samsung and won the apple's order. INFO cancels the carrier board, which can meet the number of high picks of smartphone chips and thin packages, and subsequent versions apply to a wider range of scenes. Tuo Industrial Research Institute pointed out that INFO-OS mainly facing high-performance calculations, Info-MS-oriented server and storage, while 5G communication packages are mainstream in INFO-AIP technology.
On the basis of info, COWOS, TSMC continues to deep mill 3D packages. At the Japanese VLSI Technology and Circuit Symposium held in June 2019, TSMC proposed a new SOIC package to further enhance the overall computing speed between CPU / GPU processors and memory, which is expected to achieve mass production in 2021.
TSMC can carry out package business, and even lead the development of crystal circular packages, there are two reasons for two levels. On the one hand, the wafer level package emphasizes the cooperation with the wafer, and the TSMC has a long-term technique accumulation in the wafer, which facilitates the development of a demand. At the same time, the wafer output of Taixia Electric itself can support the amount of packaging technology, and improve the input and output ratio of packaging development. On the other hand, TSMC is based on the status of the leading foundry, with talent and funding advantages.
"TSMC's position in its own industry, can gather the world's top beta talents, in the development of financial resources, more guaranteed than the general testing enterprises." The chief analyst of the core is said to the reporter.
Create a one-stop service
At the fourth quarter of 2017, TSMC stated that its COWOS was used in HPC applications, especially AI, data services, and network fields, mainly supporting production with 16nm process; Info technology mainly used for smartphone chips, and HPC and smartphones are the two sources of Ten Power 2017, of which smartphone business revenue accounts for 50%, and HPC accounts for 25%.
It is not difficult to see that the package layout of TSMC belongs to the "supporting business" of the wafer foundry. The main goal is to form a differentiated competition with other wafer foundry.
"The package and wafer manufacturing are indispensable in chip production. With the evolution of technology, the importance of packaging is continuously improved, and has become one of the core competitiveness of the foundry." Gu Wenjun "China News "Reporter said," Therefore, TSMC is developed through process technology developed from the film near the film to provide a more complete one-stop solution. "
Wang Zunmin, Tongbang Consultation Analyst, pointed out that TSMC entered the seal field, mainly to extend its own advanced process technology, through manufacturing high-order CPU, GPU, FPGA chip, and provide the corresponding beta scheme, provide complete "Manufacturing + Sparse Test" solution.
"Although the wafer is required to have additional expenses of research and development costs, this program can effectively attract high-order chip design companies to order, realize the business model of 'manufacturing, and the test is supplemented." Wang Zunmin said.
At the same time, in the latter molar era, the process is approaching the limit, and the package is increasingly attracted by the integrated circuit header.
"The nature of Moore's law is integrated with more transistors. As Moore's laws slow, manufacturers need to build more transistors in units of packages," Gartner Research Vice President, Gartner Research Due to the reporter.
"Advanced test is the growth point of the future semiconductor industry, the market prospect is broad, and the long-term voice of the semiconductor market can be accelerated to promote the advanced test layout." Wang Ruo, senior analyst of the Saidi, pointed out, "enter the advanced test market" Have high funds, technical thresholds, TSME companies can quickly seize the market for many years with funding technology. "
The high-end market of the test enterprise is squeezed
In addition to TSMC, SMIC is also based on the layout of wafer grades in collaboration with long technology. In 2014, SMIC International and Long Electric Sector Established Core Long Power, Focusing Middle Segment Silicon Watch Manufacturing and Testing Services and 3D System Integrated Chipping Business. In 2019, the core long electricity released the super-wide frequency bipolar 5G millimeters chip wafer level integrated package SMARTAIP, which realized 24GHz to 43GHz ultra-wide frequency signal transmission and reception, helping to further implement the capacity of RF front-end module integration package .
"The development direction of future testing may not be limited to the past alone, integrated solutions combined with design, materials, equipment, and the development trend of the foreigner process fusion in the integrated circuit is increasingly obvious." Wang Ruoda said.
Head vendors continue to strengthen the layout of wafer-level package, will it affect the relationship between wafers and packages?
Wang Ruoda said that the occurrence of wafer level packages blurred the boundaries between the wafer and the seal testing factory, and the foundry began to squeeze the space of the company and directly entered the high-end test.
Shengling Hai also pointed out that there was a complete division of labor between the package factory and the foundry, but in the high-end scene, the wafer factory had to develop corresponding wafer level packaging technology, and the test factory should maintain the corresponding high-end scene. Competitiveness, it also requires corresponding processes.
TSMC and other wafer makeup constitute a competition in the high-end market and the beta factory, and also requests the technical research and development capabilities of the beta plant and the corresponding capacity of the order.
"TSMC's investment in high-order test will compress a small part of the high-end market in the seal testing plant. However, in the case of the survey factor, the main market is still in other consumer electronics. In addition to active Develop high-order beta testing technology to attract customers, consolidate the order source of other wafer manufacturing plants, will be more important. "Wang Zunmin said
Reprinted from China Newsletter.
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