"Chip manufacturers are already preparing their next generation technology based on 10nm and / or 7Nm FinFET, but we still don't know how long FinFET can last, how long 10nm and 7Nm nodes for high-end devices can last, and what will happen next.
At 5nm, 3nm and smaller nodes, the semiconductor industry is also facing great uncertainty and many problems. Even today, with the increase of process complexity and cost of each node, the traditional chip size reduction is slowing down. Therefore, fewer and fewer customers can afford advanced node chip design.
Theoretically, as defined by Intel, FinFET is expected to extend to 5nm nodes（ A fully extended 5nm process is roughly equivalent to the 3nm of the foundry). No matter what these confusing node names are, FinFET is likely to die when fin width reaches 5nm. Therefore, at 5nm or more advanced nodes, chip manufacturers will need a new solution. Otherwise, the traditional chip scaling will slow down or completely stop.
For some time, chip manufacturers have explored a variety of transistors for 5nm and beyond nodes. So far, only Samsung has provided details. In May, the company launched its own technology roadmap, including the implementation of a nanosheet FET by 2020.
Other chip manufacturers also prefer similar structures within the same time frame, even if they have not publicly announced their intentions and plans. Nanosheet FET, other variants and nanowire FET belong to the category of gate all around. Other variants include hexagonal FET, nano ring FET and nanoslab FET.
[caption id=""attachment_ 238661 "" align = "" aligncenter "" width = "" 500 ""] type of horizontal surround gate Architecture [/ caption]
At present, the surround gate technology seems to be the most practical technology after FinFET. This is an evolution after FinFET. They have many of the same process steps and tools. There is a lateral surround gate technology, which is basically a lateral FinFET wrapped by the gate. Small wires or chips are used as channels.
There are other transistor options. Some chip manufacturers even seek to use advanced packaging technology for expansion. Suppliers are weighing various options and seeking the technical and economic value of each method“ FinFET can also be extended for one or two generations, "said Mark Bohr, a senior researcher and director of process architecture and integration at Intel." but the question may be 'is one of the alternative technologies a better choice? Is it a gate surrounded, III-V material or tunnel FET?' If we have to do this, we can extend FinFET. But the question is, 'is there a better choice?'
The so-called group III-V material, Bohr refers to the FinFET using group III-V material in the channel, which can greatly improve the mobility in the device. Tunnel FET (TFET) is a steep sub threshold slope device, which can operate at very low voltage.
Although surround gate technology is booming, not everyone will choose it - at least not yet“ I don't necessarily agree with that, but it did win a lot of attention. " "It's too early to predict which technology will succeed," Bohr said in an interview. But now there are enough good ideas to ensure that they can continue for several more generations. "
However, analysts believe that 10nm / 7Nm FinFET will continue in the foreseeable future. Handel Jones, CEO of international business strategies (IBS), said: "FinFET provides a combination of higher performance, lower power consumption and lower cost."
If the next generation transistor is put into production at 5nm or later, this technology will be very expensive and limited to specific applications. "It is likely to use a surround gate, but the main benefit is high performance," Jones said According to the IBS report, it will cost US $476 million to design a mainstream chip at 5nm node, compared with us $349.2 million at 7Nm node and US $62.9 million at 28nm node.
[caption id=""attachment_ 238662 "" align = "" aligncenter "" width = "" 500 ""] IC design cost [/ caption]
In order to help customers take the lead, semiconductor engineering has estimated the future situation in advance and highlighted the difficult process steps.
Different options
There are at least three main paths in the future - violent size reduction, staying at mature nodes and advanced packaging.
Those companies with sufficient funds are likely to continue to promote the traditional size reduction and realize nodes at 10 / 7Nm and beyond. Surround gate technology is the leader after FinFET, at least for now. In the longer term, there are other options, such as group III-V FinFET, complementary FET (CFET), TFET and vertical nanowires. Vertical nanowires involve stacking wires vertically.
CFET is a more complex surround gate technology in which nFET and pFET lines are stacked on top of each other. Current surround gate devices stack only one type of line, whether nFET or pFET.
CFET, TFET and vertical nanowires are more revolutionary technologies that are not expected to be realized in the short term. They will need new breakthroughs.
[caption id=""attachment_ 238664 "" align = "" aligncenter "" width = "" 500 ""] later generation transistor Architecture [/ caption]
So what will high-end players do? Gary Patton, chief technology officer of Globalfoundries, said, "7Nm will be a long-lived node. FinFET still has a long way to go. FinFET still has a lot of room to expand. "
After FinFET, there are many options in R & D. For example, global foundries is exploring nanosheets, nanowires and vertical nanowires.
The decision and timing of a technology depend on various technical and economic factors“ You should strive to develop a process that can produce and provide a value proposition. " "It's not as intuitive as it used to be," Patton said. Much more scrutiny is needed. "
In fact, a technology may continue to be in the R & D stage for ten years. Then, according to a series of indicators, the best technology comes to the market and other technologies collapse.
But it is certain that not all companies will need FinFET and nanowires. Most of them will stay at the nodes of 22nm planar process or above. Many companies cannot afford FinFET, and analog and RF devices do not need this technology.
"10nm, 7Nm and 5nm sound attractive." Walter ng, vice president of business management at UMC, said, "but how many companies can really afford and earn back the design and manufacturing costs? Only a few companies can really push forward the demand. "
But companies at 22nm and higher also face some challenges“ Every other company needs to know how they can continue to compete. " "They are trying to find a way to achieve differentiation and reduce costs," Ng said
So many companies turn to advanced packaging. All chips need IC packaging. For example, customers can use traditional packaging, such as flip BGA. Advanced packaging is an extension of this idea. Multiple dies are integrated in the same package to create high-performance systems. 2.5d/3d and fan out are representatives of such methods.
So who will be the ultimate winner in this market? David fried, chief technology officer of coventor, said, "there is no answer yet. People are really looking for applications to drive practical solutions. "
Fire points out that there is no one solution for all applications. For example, FinFET or subsequent technology transistors can be used in high-end microprocessors“ But for Internet of things devices, this may be the wrong direction. " "There is no single application that can drive the whole market," he said. People must stop looking for answers once and for all. Many different technologies can succeed at the same time, but they are aimed at different applications. "
Fried predicted, "I guess 7Nm seems quite revolutionary. It will be FinFET. If we see other technologies other than FinFET, it may be at the 5nm node. But remember, the lateral gate all around nanowire device is like a FinFET with two additional etchings. From FinFET to laterally encircling gate nanowire devices is quite revolutionary. I hope we can start seeing it at the 5nm node. Besides, we don't have much visibility. "
Transistor trends and processes
Now FinFET is the cutting-edge transistor technology. In FinFET, the current control is realized by realizing a gate on each of the three sides of fin.
Gate pitch is a key index. The gate spacing of Intel 10nm FinFET technology is 54nm, and the gate spacing of 14nm technology is 70nm（ Intel's 10nm is equivalent to 7Nm of Foundry).
When the gate spacing is close to 40 nm, a major decision is required. According to IMEC's simulation, FinFET began to approach the gate spacing of 42 nm. "Nanowires will expand downward and still have good electrostatic control," said an steegen, executive vice president of semiconductor technology and systems at IMEC According to IMEC, nanowire FET has shown good electrostatic control ability at 36 nm gate spacing. IMEC has also designed a nanowire with a diameter as low as 9 nm.
[caption id=""attachment_ 238665 "" align = "" aligncenter "" width = "" 279 ""] micro nanowires of IMEC [/ caption]
Generally speaking, surround gate can provide better performance than FinFET, but there are also some problems, namely driving current and parasitic capacitance. Combining these problems is a relatively new layer called middle of line (mol). Mol uses a series of contact structures to connect separate transistors and interconnects. In mol, parasitic capacitance is a problem. It will bring external resistance to all parts of the device. This includes contact with the junction where the low resistance Schottky barrier and silicide are located.
One version is the transverse nanowire FET, in which you cut a FinFET into pieces, and each piece becomes a tiny horizontal nanowire, which is used as a channel between the source and drain.
Other common variants include nanosheets or nanoslab FETs. Both technologies are similar to transverse nanowire FET, but the wire is much wider and thicker.
Each variant has its own advantages and disadvantages. Intel's Bohr said: "(nano chip FET) is not as revolutionary as it sounds. It's just a laterally placed FinFET. I'm not sure if it's as valuable as nanowires. "
In the nanowire FET, the whole line around the gate can achieve better control of the gate. "It is this improved gate control that allows you to continue to extend the gate length," said Mike chudzik, senior director of Applied Materials transistor and interconnection group
As mentioned earlier, FinFET is cut into pieces. Therefore, the surface area on the device will be reduced. Chudzik said, "you are losing the dividends of silicon itself. I'm sure you can benefit from the cut-off current, but there will be shortcomings in the overall drive current. "
Therefore, nano chip FET is also reasonable. He explained, "this is where you start extending these lines. You need to get more driving current. In addition, you can also adjust the shape of these wires or chips to help reduce the capacitance. "
Another version called nano ring FET has similar advantages. "The whole idea of nano ring is actually to squeeze the chips together a little, which can effectively reduce the capacitance," he said
The first surround gate device is likely to have three wires. But over time, chipmakers will need to stack more wires to provide more performance. "We certainly don't want to introduce a new device architecture that can last only one node," he said（ So our idea is to consider stacking more nanoplates. But you can't just stack channels indefinitely, because you will encounter a lot of the same parasitic, capacitance and impedance problems, as you will encounter in higher FinFET. "
As a harbinger of the future, global foundries, IBM and Samsung recently published a paper on 5nm and 3nm node nano chip FET; It is said that this technology can get better performance on smaller footprint than FinFET.
[caption id=""attachment_ 238668 "" align = "" align center "" width = "" 500 ""] (a) FinFET, (b) nanowire (c) cross section simulation diagram of nanosheet [/ caption]
Extreme ultraviolet (EUV) is used for some layers
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