"For example, driven by the popularity of live broadcasting of sports events and computer games, 4K video and h.265 coding algorithm have ushered in great development, and the traditional CPU is difficult to cope with the required frame rate. Similarly, artificial intelligence is also using massive data for training neural networks to learn and identify patterns in data, and then used in many different applications such as image recognition, automatic driving, search optimization and natural language translation. In these two areas, data centers increasingly use special accelerators to achieve low latency response to user queries.
Intel: We support the ARM kernel
At the Intel SOC FPGA Developer Forum (ISDF) held in November 2016, Yang Xu, global vice president and President of Intel (Intel), once again made a decision to the industry, including investing in new FPGA and SOC FPGA products, supporting a longer product life cycle, and continuously providing customers with first-class service and support And continue to support the four commitments including ARM core in Altera SOC FPGA.
He said that today's technology is constantly "breaking the barriers between the digital world and the real world". Intel calls the relationship between things, devices and cloud a "virtuous circle of growth". Through this cycle, a series of technologies enhance their value and promote Intel to constantly adjust its own strategy. The uniqueness and flexibility of FPGA play a very differentiated role in the field of intelligent connection, which is the fundamental reason why Intel is willing to spend $16.7 billion to acquire Altera.
According to the plan, the development roadmap of Intel's next-generation FPGA and SOC FPGA products will be divided into three product platforms (Figure 1) of low, medium and high, and support Intel Architecture (IA) integration. Among them, low-end products are mainly used in industrial IOT, automobile and community RF fields, using Intel 22nm process technology; Midrange products are mainly used in 4.5g/5g wireless, UHD / 8K broadcast video, industrial IOT and automotive fields, using Intel 10nm process technology; High end products are mainly used in the fields of cloud and acceleration, terabit system and high-speed signal processing, using Intel 10nm process technology.
Figure 1: Intel next generation FPGA and SOC FPGA development roadmap
Intel promises to provide different heterogeneous architectures according to different customer needs, including discrete CPU + FPGA, encapsulated integrated CPU + FPGA, and FPGA integrating Intel CPU / FPGA / arm.
As the most powerful FPGA product of Intel at present, all models of Stratix 10 FPGA / SOC FPGA series adopt heterogeneous 3D SIP integration technology, and integrate high-density single-chip FPGA core logic, high-speed serial transceiver and protocol block by using Intel dedicated embedded multi-core interconnect bridge (emib) technology. In addition, the series is also the first device to adopt the new hyperflex architecture. By introducing registers on all core interconnection line segments, Stratix 10 series can effectively reduce wiring delay and improve overall performance.
Xilinx: reconfigurable acceleration stack improves computing efficiency by 2-6 times
As the inventor of FPGA technology, Xilinx has made great progress in data center applications in the past few years. According to the relevant information provided by Steve Glaser, senior vice president of Xilinx strategy and marketing department, at present, three of the world's seven super large-scale cloud service companies have adopted Xilinx FPGA, of which Baidu announced the design of Xilinx ultrascale FPGA pool in October 2016 to speed up machine learning inference; In May 2016, Xilinx joined hands with AMD, arm, Huawei, IBM, mellanox and Qualcomm to establish the intelligent cache consistency interconnection standard (ccix) alliance. Five months later, the number of members has surged to three times that at the beginning of its establishment; In November, Xilinx released the latest 16nm virtex ultrascale + FPGA product using high bandwidth memory (HBM) and ccix technology, which not only increased the memory bandwidth by 20 times, but also reduced the power consumption per unit bit by 4 times.
However, FPGA has always been difficult to program, and relevant personnel need to have both software and hardware skills. In order to better meet the needs of emerging markets, following the release of sdaaccel software definition development environment for FPGA acceleration in 2014, Xilinx launched reconfigurable acceleration stack at the end of 2016 for the three fastest-growing computing intensive applications in the field of super large-scale data center: machine learning, data analysis and streaming video live broadcast.
This means that Xilinx will provide not only FPGA chips, but also optimized mathematical function library and application function library (such as cafe for machine learning), software framework implementation scheme, tools supporting high-level languages such as OpenCL and C / C + +, openstack support for easy configuration and management, and expected accelerator board reference design. Andy Walsh, director of strategic market development of Xilinx cloud computing, said that through Xilinx FPGA, the reconfigurable accelerated stack scheme provides the industry's highest computing efficiency 40 times higher than x86 server CPU and 6 times higher than competitive FPGA scheme. By switching to the best designed bitstream, the optimization of these workloads can be completed in milliseconds.
"An accelerator may be fast under a specific workload, but it must also see whether it can reduce the overall operating cost of the data center." Andy Walsh explains that there are two decisive factors in the total cost of ownership of acceleration technology: the breadth of applications that accelerators can support, and how accelerators can be easily and efficiently configured and pooled to determine the utilization of accelerators.
Figure 2 lists the different options for accelerating data center workloads: CPU, custom ASIC, GPU, and FPGA. According to Andy Walsh, although GPU and custom ASIC also adopt pooled configuration deployment to improve utilization, neither can support a wide range of applications. Due to the lack of reconfigurability, they can only support workloads matching their fixed hardware architecture. In addition, the huge design investment, design risk and design cost brought by creating custom ASIC make it very uneconomical and economical compared with FPGA.
As for the strategy of integrated CPU FPGA design proposed by Intel, he believes that this scheme limits the breadth of applications and the utilization of accelerators, making it enter "no man's land". This CPU + FPGA device is limited by power density, which usually limits FPGA to medium and low-end devices and limited workload. FPGA integration in the CPU suite will also limit the ability of the pooled accelerator, thus greatly reducing its utilization.
Figure 2: differences in application breadth and utilization of different schemes for accelerating data center workload
"Altera emphasizes floating-point precision DSP, which does not match many applications, including machine learning inference, and is far lower than the computational efficiency of GPU optimized for training." Andy Walsh said that in terms of computing efficiency, Xilinx FPGA is 2-6 times higher than Altera independent FPGA, and its utilization rate is greatly improved compared with Intel Integrated MCM. Its advantages stem from its excellent DSP architecture, memory hierarchy and leading position in chip technology.
Figure 3: differences in utilization and computing efficiency of different schemes for accelerating data center workload. Read the full text and the technology zone
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