1. How to avoid crosstalk in PCB design?
The change signal (e.g., step signal) is propagated along the transmission line, and the coupling signal is generated on the transmission line CD, and once the signal is ended, the signal is restored to a stable DC level, and the coupling signal does not exist, so crosstalk Only in the process of signal jump occurs, China IC37 network and the change in signal edge (conversion rate), the larger the crosstalk. The electromagnetic field coupled in the space can extract a set of countless coupling capacitors and coupling inductors, wherein the crosstalk signal generated by the coupling capacitance can be divided into a forward crosstalk and reverse crosstalk SC, the two signals; coupling The crosstalk signal generated by the inductor is also divided into forward crosstalk and reverse crosstalk SL, which is opposite to the two signal poles. The forward crosstalk and reverse crosstalk generated by coupled inductance capacitors are present, and the magnitude is almost equal, so that the forward crosstalk signal on the victimized network is opposite to the polarity, mutual cancellation, and the reverse crosstalk is the same, and superimposing enhancement. The mode of crosstalk analysis typically includes default mode, tri-state mode and the most bad Chinese ICPDF network condition mode analysis. The default mode is similar to what we actually on the crosstalk test, that is, the network driver is driven by flip signal, and the victimized network driver maintains the initial state (high or low), and then calculates the crosstalk value. This approach is more effective for the crosstalk analysis of the one-way signal. The triangular mode means that the three-state terminal of the inversion signal is driven by the flip signal, and the crosstalk size is detected. This way is more effective for two-way or complex topology networks. The worst case analysis refers to the initial state of the drive of the victim network, and the simulator calculates the sum of all default infringement networks to each victim network. This approach generally only analyzes individual critical networks because there are too many combinations to calculate, and the simulation speed is slower.
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2. Is there a regular basis for the copper area of the ground plane of the microstrip line?
For microwave circuit design, the area of the ground plane affects the parameters of the transmission line. The specific algorithm is more complicated (see Anjun's Eesoft). The transmission line simulation of the general PCB digital circuit is calculated that the floor surface area has no effect on the transmission line parameters, or ignores the impact.
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3. The harmonic exceeding the clock signal is found in the EMC test, but the decoupling capacitor is connected to the power pins. What do you need to pay attention to in the PCB design to suppress electromagnetic radiation?
The three elements of EMC are radiation sources, propagation pathways and injured. The transmission route is divided into spatial radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power decoupling is the propagation of the transmission method, in addition, the necessary matching and shielding are also required.
4. Why is it a double-sidedly, some is not?
There are several aspects of the role of the floor: 1. Shielding; 2, heat dissipation; 3, reinforcement; 4, PCB process processing needs. So no matter how many layops are placed, you must first look at its main reason. Here we mainly discuss high-speed issues, so mainly said masking. The surface is beneficial to EMC, but copper should be complete, avoiding island. Generally, if there are many wirings of the surface device, it is difficult to ensure the complete copper foil, and the inner layer signal is span segmentation. Therefore, it is recommended that the surface device or a pair of plates are not paved.
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5. For a set of bus (address, data, command), multiple (up to 4, 5) devices (Flash, SDRAM, other peripherals ...), use that way when PCB wiring is available?
The impact of the wiring topology on signal integrity is mainly reflected in the signal arrival time on each node, and the reflected signal is not consistent with a certain node, so that the signal quality is deteriorated. In general, the star topology can control the signal transmission and reflection delay by controlling the same long STUB, reaching a better signal quality. Between the topology, take into account the signal topology node, actual working principle and wiring difficulty. Different buffers are inconsistent with the reflection effects of the signal, so the star topology does not have a good delay in which the above data address bus is connected to the flash and sdram, which cannot ensure the quality of the signal; on the other hand, the high-speed signal is generally Communication between DSP and SDRAM, the rate at the time of FLASH is not high, so as long as the actual high-speed signal is effectively operated, it is not necessary to pay attention to the waveform of the Flash; the star topology is compared to the daisy chain and other topologies Speaking, the wiring is difficult, especially a large amount of data address signals, using a star topology. The drawings are simulated waveforms when DDR - DSP - Flash topology connections, and DDR-Flash-DSP connections using the HyperLynx simulation data signal. It can be seen that the second case, the signal quality of the DSP is better, and the Flash is poor, while the actual working signal is the waveform at DDR.
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6. Is the PCB of 30m or more, use the automatic wiring or manual wiring when the wiring; the software function of the wiring is the same?
Whether the high speed signal is based on the signal rising edge rather than absolute frequency or speed. Automatic or manual wiring should be supported by software wiring function, some wiring can handle more than automatic wiring, but some wiring, such as checking the distribution line, the bus time delay compensation wiring, the effect and efficiency of the automatic wiring will be much higher than the handmade wiring. Generally, the PCB copy plate substrate is mainly composed of resin and glass silk cloth, since the ratio is different, the dielectric constant and thickness are different. The general resin content is high, the smaller the dielectric constant, and can be thinner. Specific parameters, you can consult with the PCB manufacturer. In addition, as new processes appear, there are also some special material PCB boards to provide them to such as ultra-thick backplanes or low loss grungers.
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7. In the PCB design, the ground wire is usually divided into protective land and signal ground; the power supply is divided into digitally and simulated ground, why should it be divided on the ground?
The purpose of division is mainly for EMC, worrying that the digital partial power supply and the upper upper noise will interfere with other signals, especially analog signals through the conductive pathway. As for the division of the signal and the protection of the ground, it is because the consideration of ESD static discharge in EMC is similar to the role of the lightning rod ground in our lives. In any case, there is only one in the final land. It is only different from noise. 8. Is it necessary to add a ground shield on both sides when cloth clock?
Whether to add the mask to determine according to the crosstalk / EMI situation on the board, and if the processing of the masked ground is not good, it may make the situation even better.
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9. What is the corresponding countermeasure when the clock lines of the cloth?
For clock lines, it is best to perform signal integrity analysis, formulate corresponding wiring rules, and wiring according to these rules.
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10. Is the PCB single layer board handwired, is it placed on the top or bottom?
If it is a top layer, the bottom wiring.
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