1 Introduction
Most mobile TV standards use OFDM technology, but for OFDM signals, carrier frequency offset will destroy orthogonality asking the signal subcarrier, introducing carrier interference interference. A small frequency is likely to cause the SNR to decrease, so in the OFDM mobile TV system, it is very important to accurately estimate the carrier frequency deviation.
Taking the DVB-H system as an example, integer multiplication is used to perform related estimates by continuous pilot, and the decimal multiplier is used to correct the algorithm combined with the analog value by integer multiplier preferences. Hardware implementation architecture.
2. Carrier synchronization scheme based on DVB-H
The algorithm of the system carrier synchronization is generally known information in the base F signal frame structure. Taking the DVB-H system as an example, the known information in the signal frame structure is a time domain cyclic prefix CP and continuous pilot and discrete conductance that appear on the frequency domain. Therefore, the value of the decimal carrier frequency offset is typically used in front of the FFT, while the value of the integer multiplier frequency or discrete pilot is detected by continuous pilot or discrete pilot frequency after the FFT. However, this traditional algorithm is finely estimated to calculate the calculation of the frequency of the small double carrier frequency, and the hardware is complex. This article uses a cyclic prefix to estate a decimal multiplier frequency, and the FFT is used to use continuous pilot estimation integer multiple times, and the scheme for correction of the decimal multiplier offset, simplify the juice calculation complexity, easy hardware Implementation, this program considers the implementability of estimated accuracy and hardware, as shown in Figure 1.
The estimated value ε obtained by the consecutive N frame is performed by the average module on the rapid capture of the decimal N-frame, and further reduces the effect of the random noise by the average module. After the FFT, the integral multiplier frequency is corrected by the continuous pilot signal of adjacent two OFDM symbols on the frequency domain, and it is judged whether or not the decimal multiplier wave frequency is ± 0.5, estimated on the time domain. Duplex double offloads. The integer multiplier frequency output of the frequency domain estimate is fed back to the time domain end of the received signal, and the carrier frequency offset compensation is added to the decgalence value after the average module.
2.1 small double carrier frequency deflection calculation
At the sender, the cyclic prefix is a copy of the last part of the valid data per frame, as shown in Figure 2. The cyclic prefix is the same as the last part of the valid data of each frame, and the difference is a phase rotation, which is proportional to the carrier frequency offset, which can be estimated according to this phase rotation estimate to obtain a decimal double load wave frequency.
The specific algorithm is related to the use of the cyclic prefix opening with the data, to minimize the possibility of contamination of the previous frame, the more the position of the window is, the better. Related values During the windowing range, the average phase is taken and then divided by -2π, which can be estimated to be estimated in the case of multipath channel.
Where: ω is the window length.
2.2 integer multiplier frequency deflection rate
After the decimal multiplier offset is estimated and compensated, the carrier frequency offset a main influence on the cyclic shift of the subcarrier, which can be performed using continuous pilots in a specific subcarrier position in each frame of OFDM symbol. Estimation of carrier frequency offset. Since the continuous pilot occurs in a fixed position in each frame, the continuous two frame OFDM symbols are subsequently related to the position of continuous pilot, using a sliding window for long S. Upper subcarriers have a possible relative offset range, which gives the S correlation value, where the maximum correlation value corresponding to the relative offset of subcarriers on the frequency domain, that is, an integer multiplier frequency offset estimate
The complex value of the symbol is higher; S is an estimated range of integer multiplex (S is the window movement value, s ∈ s; S-road correlation and maximum CM corresponding to integer times The estimated value of the carrier frequency offset.
2.3 Data Frequency Wave Frequency Defiat Correction Algorithm
If the decimal time is within ± 0.5, only the estimated value of the 2.1 section is likely to be hop compared to the actual value, that is, +0.5 is estimated to be
Where: μ is a pre-set threshold, generally set to 0.2, and the intensive multiplier estimation is required to compensate for the decimal factor of the quadrature offset, and the remaining decimation is between -0.25 ~ + 0.25, This avoids the possibility of extortion of ε existence of extortion in +0.5 in +0.5 to increase the accuracy of the estimate.
3, hardware implementation of DVB-H carrier synchronization
3.1 Hardware implementation of small double carrier frequency offset estimation
According to the algorithm principle and formula (1) described in claim 4, it is assumed that the opening length is ω, the OFDM symbol is as a NC, each valid data is k bit, for each OFDM symbol 4 × W Multiplication, 2 × ( Ω-1) times, while two RAMs, each capacity is NS × K bit, a block stores the current OFDM symbol, and the other for reading the content of the previous OFDM symbol. The hardware architecture of FIG. 3 takes into account the time interval between each estimate (the length of the cycle prefix CP) is sufficient, so it can be multiplexed for RAM. At the same time, the multiplier is multiplexed by selecting the control signal, and only one multiplier can be implemented.
First, the control signal is generated, and the real part of the data within the window is selected, and the imaginary portion is sequentially stored in the FIFO length 64, and the window length is set to 64. According to the control selection signal SEL, the following 4 sets of signals will be sent in the following 4 sets of signals.
The accumulator 4 is accumulated. After a frame estimation, the value of the accumulator 1 and the accumulator 4 and the value of the accumulator 4 were re-applied to the adder to obtain an estimated real part of the accumulator 2 and the value of the accumulator 3 to obtain an estimated imaginary portion. Then average the estimated value, for hardware implementation, the window length is selected to 64, so the result is sent to the shift to the right and 6 digits, that is, the accumulation result can be averaged. Finally, the estimated values of the continuous 8 frames are performed by the accumulator shifter and right to move 3 digits, further reducing the effects of random noise. Table 1 compares the hardware resources of this design and traditional related architecture.
As can be seen from Table 1, the architecture of this document is half the amount of memory capacity, especially the multiplier resources that are very scarce in FPGA, saving 4W-1, the longer the number of related windows, the larger the number of related windows.
3.2 Integer multiplier estimation and hardware implementation of decimal multiplier correction
For integer multiplier frequency offset estimation, input data removes the cyclic prefix CP, and then the frequency domain data is obtained by FFT, and the continuous pilot or discrete conductance estimation carrier frequency is used, both are related methods. Table 2 Compares the case of hardware resources required for continuous pilot and discrete conductance.
Table 2 is a number of subcarriers in one OFDM symbol; m is the number of subcarriers included in the discrete conductor cycle; k is the number of bits of each subcarrier signal; Q is a continuous pilot in one OFDM symbol. The number of numbers; P is the number of discrete pilots included in the discrete conductor cycle, and S is the sliding correlation window. There are generally M "N, P" Q, so the algorithm of the discrete intersection multiplier frequency offset estimate is more than the continuous pilot estimation algorithm to use more memory, multiplier, and adder resources. The method of continuous pilot can have accurately estimate the integer multiplier frequency offset, and no need to use the discrete pilot algorithm to perform integer multiplier frequency offset estimation.
For decimal multiplier frequency prefers, if the decimal value is within ± 0.5, the estimation value and the actual value may have a jump compared to the actual value, to be accurately estimated, usually many OFDM symbols utilize continuous pilot Or discrete pilot performs fine estimation. This paper is combined with the decimal multiplier estimation by integer multiplier estimation and the estimated value, which uses the integrated multiplier frequency offset estimation, and by reasonable setting parameters, only one The shifter, an adder and a comparator can greatly save the amount of operations under the premise of maintaining certain precision.
The IV in Table 3 is a sub-carrier number of quadrature multiplier deflection by continuous or discrete pilot; k is the number of bits of data; T is a continuous or discrete number of secondary modifications for performing an estimation. From Table 3, it can be seen that the use of continuous pilot or discrete pilot pairs of decimal multiplier frequency is subjected to fine estimation, and hardware implementation is complicated, and resources are consumed. The use of this paper can greatly save hardware resources through integer multiplier estimation correction algorithms. The hardware implementation frame of integer multiplier frequency offset estimation is shown in Figure 4. First, send the input data sent to the selector to remove the cyclic prefix CP, send people
FFT module; for the speed of operation and continuity of data using ping-pong operation, in the first buffer period, the continuous two frame data is cached to the data buffer modules 1, 2, and it is selected by the input data selection signal in the second buffer cycle. The two frame data cache data buffer modules 3, 4, simultaneously deposit the data operation module of the data buffer module L, 2 in the first buffer period, and perform operations. The specific operation process of the arithmetic module is as follows: The continuous two frame signals are stored in the RAM of the two depths of 4 096, and the number of consecutive pilots within the sliding related window is read in turn, and the number storage registers are related. For example, in Figure 4, 5 bits left for a set of continuous incorporations, and C. Send a subtractor, the comparison of the symbol bit can result in the result of frequency offset compensation.
3.3 Hardware implementation of carrier frequency offset compensation
The integer multiplier frequency bias estimate obtained by the frequency domain estimate feeds back to the time domain end of the received signal, and adds ΔF to the decimal value of the decree after the average module. The metaded compensation on the time domain is multiplied by an opposite phase α, which can be derived
First, the estimated carrier frequency is fed by the accumulator, the sampler, and the multiplier.
Then, then calculate the sinusoidal, cosine value, and finally compensated according to the formula (4), (5), and the homographic value is sent to the value obtained by the cosine value into the multiplier delivery register 1, and the orthogonal component and the sine value Feed the multiplier, the obtained value is sent to the register 2, the value of the register 1 and the register 2 is sent to the adder to obtain the same phase component of the non-carrier frequency offset; the orthogonal component is sent to the cosine value to the multiplier to feed the register 3 At the same time, the same phase split is sent to the value of the value obtained from the sinusoid value to the multiplier to feed the register 4, and the register 3 and the value of the register 4 are transmitted into the orthogonal component of the unloaded frequency offset.
The calculation of the sinusoidal and cosine values is used instead of the lookup table to ensure that storage resources are greatly saved under conditions of certain precision. Figure 6 is a CORDIC hardware implementation framework.
4, small knot
Based on the existing algorithm, the DVB-H system is used as an example, and a program and hardware implementation architecture is proposed for its carrier synchronization. The above architecture is implemented using the Verilog hardware description language, simulated with Modelsim SE5.7 while using Quartus II 6.o, using chip EP2C70F672C8. The highest clock frequency of the integer multiplier frequency is more than 87 MHz, and the M4K used is 48, and the Le is about 3,800, the multiplier is 12; the decimal multiplier frequency bias estimation module is up to 102 MHz. The M4K used is 2, which is about 184, and the multiplier is 1; the maximum clock frequency of the carrier frequency partial compensation module can reach 73 MHz, and the LE used is about 2,000, and the multiplier is 8. The hardware implemented in this article, fast, saving hardware resources.
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