Atria Logic developed H.264 codec IP (including AL-H264E-4KI422-HW encoder and AL-H264D-4KI422-HW decoder) grafted onto Xilinx Zynq Z-7045 SoC, enables UHD 4K @ 60fps video flow operation, as shown below:
ArTIa Logic developed H.264 codec IP design block diagram
ArTIa Logic Design AL-H264E-4KI422-HW encoding IP core is hardware-based, feature-rich, low-latency, high-quality, for H.264 (AVC) UHD Hi422 intra-frame coding. AL-H264E-4KI422-HW encoder AL-H264D-4KI422-HW paired low-delay decoder.
The IP core comprising the following features:
Full modular design, allowing users to customize and extend
Support frame and H.264 encoding and decoding Hi422 5.1
Receive and transmit subsystem integration HDMI2.0
Support for 10-bit codec
Supports RGB, YUV 4: 2: 2/4: 4: 4
~ 0.3 seconds latency
It supports variable bit rate (VBR) and constant bit rate (CBR) mode
Video Quality 0.99% SSIM, or 50dB PSNR or higher
Video processing subsystem for pre / post processing, including color space conversion, video scaling, and concentration subsampled
Support Gbps Ethernet data stream output
We need to design a program to evaluate our UHD encoding and decoding IP core to meet the 4K @ 60fps performance needs, then we need a flexible and powerful platform. Eventually we chose Xilinx ZC706 Evaluation Kit, which is based Zynq Z-7045 SoC, for the following reasons:
There is a ready-FMC expansion boards to provide 4K HDMI Video Interface: TB-FMC-HDMI 4K 2.0 version daughter card
Zynq Z-7045 SoC rich programmable logic resources can accommodate the encoder and decoder logic IP, in order to meet the strict timing requirements required performance
Zynq SoC processor system integrates a dual-core processor ARM Cortex-A9 MPCore, allows us to have the ability to modify and customize application-driven software design, application design such a GUI Interface
H.264 encoder supports H.264 Hi422 format configuration, a standard 5.1 (3840x2160p30) unique intra-coded. Support for 10-bit video stream from the video to bring this article to see the representation does not appear gray and color degradation. Support YUV4: 2: 2 video stream means being able to achieve better color division - especially for red clear - this makes the image clearer. Very important occasion for medical imaging video quality.
Atria Logic Corporation UHD H.264 encoder block diagram IP
Intra-coded so that the frame rate implemented H.264 encoder delay, pipeline architecture macroblock to further reduce the delay: about 0.3 msec. Pipeline design supports eight pixels per clock processing, to achieve real-time 4K @ 60fps video encoding.
Atria Logic developed this H.264 encoder uses only Zynq Z-7045 SoC 78% of programmable logic and DSP resources, and 55% of the available RAM, sufficient space reserved for the other necessary circuitry.
H.264 decoder configuration format support H.264 Hi422, 5.1 standard (3840x2160p30) unique intra-coded. Like support the same encoder 10 encodes a video stream that brought the video to see the article does not appear gray or color degradation. The decoder also support YUV 4: 2: 2 video format, to support intra-decoding, using frame rate pipelined architecture for the decoder delay.
Atria Logic Corporation UHD H.264 decoder block diagram IP
For any closed loop of human / machine applications low latency is very important. When AL-H264E-4KI422-HW encoder and AL-H264D-4KI422-HW latency decoder connected through an IP network, a glass delay time is about 0.6 milliseconds (not including transmission time). This is about two frames of delay time.
Atria Logic H.264 achieved only with a decoder Zynq Z-7045 SoC 68% of the programmable logic resources, 35% of DSP resources, and 45% of the RAM, a circuit necessary for the other leaving a sufficient space.
HDMI subsystem comprises two main modules: Xilinx LogicCore HDMI TX and RX subsystem, as shown below:
HDMI transceiver (GTX) module for transmitting and receiving the TX and RX HDMI serial data transmission, and converts parallel data stream prior to the serial data stream and sheet. Transceiver modules perform mutual conversion between parallel data and serial data is in a high-speed Zynq SoC GT HDMI PHY transceiver as physical layer interface.
TX subsystem includes a transmission module, AXI Video conversion, video and optional HDCP timing control module. Axi Video data transfer clock for each flow channel of two to four sub-pixels to HDMI TX, 8,10,12 and supports encoded data bits. This data stream conforming to the AXI Design Reference Manual (UG761) protocol defined in the video transmission, video converter input module AXI-Stream converted to the local video format, video timing controller for generating a local video timing. AXI Stream Audio multi-channel uncompressed audio data to the HDMI TX subsystem. HDMI TX transmission subsystem module Zynq Z-7045 SoC ARM Cortex-A9 of the control processor via the CPU interface.
HDMI RX subsystem includes three AXI protocol interface. The captured video converter bridge is converted into local video AXI Stream data stream, the video data output by the interface Connections Video AXI, AXI protocol specification compliance Design Reference Manual (UG761) defined. Video timing controller video timing is measured, the received audio sent through the audio interface AXI Stream. Communicate with the CPU interface control and status data peripherals.
HDCP module is optional, not included in the standard IP core configuration. Technology area
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