Multiplication DAC is an ideal construction module for waveforming applications. Because the R-2R architecture of the multiplication digital-tote converter (DAC) is very suitable for low noise, low glute, rapid establishment.
When there is a waveform from a fixed reference input voltage, some important AC specifications must be considered, including establishment time, intermediate glitch, and digital SFDR.
Today we come to analyze these important DAC specifications related to waveforms.
Establishment time
Suppose the DAC is driven by a real broadband low impedance signal source (reference voltage and ground pin), it will be established quickly. Therefore, the pressing rate and setup time of the multiplication DAC are mainly determined by the operational amplifier. Determine the specifications of the operational amplifier AC performance include its input capacitance (must be minimized) and 3 DB small signal bandwidth. Note that the bandwidth of the operational amplifier is limited because it must drive a large load of the DAC feedback resistor. For example, 10 kΩ feedback resistors are a considerable load that is the primary pole of determining the circuit configuration bandwidth.
Figure 1. 100 ns establishment time
Intermediate level burr
For R-2R structures, the main burrs caused by code change occurs when a 1 LSB changes around the intermediate level. In a 12-bit system (such as DACAD 5444), the intermediate level change is from 7FFH to 800h or from the code from 800h to 7ffh. If the burr is very serious, it may adversely affect the motor / valve / actuator control application. When the multiplication DAC attempts to becomes 800h from 7FFH, the MSB switching speed of the DAC is lower than the switching speed of other bits. Therefore, the DAC sees 000h in the few nano seconds before the MSB switching to 1. The yellow curve shown in Figure 2 is the case; before the MSB switching and pulling the DAC output back to 800h, the output is output toward 0 V.
Figure 2. Intermediate level burr
Digital SFDR
No stray dynamic range (SFDR) refers to the available dynamic range of DAC, exceeds this range, and stray noise will interfere with the fundamental wave signal or distortion. The difference between the maximum harmonic or non-harmonic-related straduated in the basis of the fundamental wave and the DC to the entire range (half of the DAC sampling rate). Narrowband SFDR measures SFDR within any window range. The ideal sine wave has countless points. However, the sine wave generated by a digital manner is limited by the fixed update rate and the DAC resolution. The number of points per cycle is given by the following formula:
in :
N = sampling point number
CLOCK = DAC update rate
Fout = output frequency of the generated waveform
Figure 3 shows a 20 kHz sine wave generated by 1 MHz using 12-bit AD5444, with 50 sample points per cycle. The maximum update rate of the AD5444 is 2.7 MSPS. To generate more waveforms, you must use a faster update rate. The AD5445 of the parallel interface provides the maximum update rate of 20 msps.
Figure 3. Broadband SFDR, Fout = 20 kHz, clock = 1 MHz, reading full text, original title: How to output waveforms, look at these specifications
Article Source: [Micro Signal: Analog_Devices, WeChat Public Number: Jia Nan Technology] Welcome to add attention! Please indicate the source of the article.
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