All reset signals on the main board of the reset circuit are generated by the chipset, mainly generated by the South Bridge (internal reset system controller) or reset generator (74H series chip), that is, all of the motherboard needs to be reset. The equipment and modules are reset by the South Bridge. Nanqiao wants to generate a reset signal or say that the South Bridge wants to reset other devices and modules, which must first reset themselves or have a reset source. Make the South Bridge reset or say that the reset source of the South Bridge is the gray line of the ATX power supply (the gray line is normal is 5V level, the working is a constant 5V, the gray line of the ATX power supply is also a PG signal), or the system power management chip The PG signal is sent.
Working principle of power-on reset circuit
Many ICs contain POR circuits
(Power-on reset, Power-on Reset)
(Power-on reset, Power-on Reset)
(Power-on Reset, Power-on Reset)! Important things say three times!
Its role is to ensure that the board is powered on, the analog and digital modules are initialized to a known state.
POR three steps: The power supply voltage reaches the threshold voltage - the POR circuit will release the internal reset signal - the state machine starts the initialization device.
Before initialization is completed, the device ignores external signals, including transmission data. The only exception is a reset pin, which will use the POR signal inside.
What is the length of 1.1por circuit?
Popular popular popular science, window comparator: Commonly composed (dual comparator), there are two threshold voltage Vt2 (high threshold voltage) and VT1 (low threshold voltage), if VT1 ≤ Va ≤ VT2, VOUT outputs high; if VA
VT2, VOUT outputs a low level.
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Dual compalar
The POR circuit can be represented as a window comparator, that is, once the operating voltage is between the high and low threshold, the circuit is automatically reset. as the picture shows.
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Simplified POR circuit
How to operate 1.2por?
The comparator window is usually defined by a digital power supply level. The digital module controls the simulation module, the voltage required for the digital module is similar to the minimum voltage required for the operation of the simulation module.
Higher VT2 thresholds will be better to the analog module. If the recommended minimum supply voltage is too close, the reset may be unexpected when the voltage is slightly lowered.
If the device includes a stand-alone analog power supply and a digital power supply, a policy that avoids the fault is to increase a POR circuit to keep the two modules reset state until the power supply voltage is sufficient to ensure that the circuit is working properly.
1.3por how to deal with short power-off?
The POR circuit sometimes integrates a power-down detector (BOD) that prevents the circuit from reset when the voltage is very short-proofed. In fact, the threshold voltage defined by the power-down circuit has increased hysteresis, usually from about 300 mV. BOD guarantees that when the power supply voltage drops below VT2, the POR does not generate the reset pulse unless the supply voltage dropped to another threshold VBOD (VT2-300MV), as shown.
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Power-off detection
The power-down threshold level is enough to ensure the digital circuit reserved information, but it is not enough to ensure its normal work. In this way, if the power supply is only very short, the controller can abort the activity when the power supply drops below a level, so that the entire device is from reinitialization.
1.4 Three cases to be mastered correctly
First, the monocular power supply is oscillation
The actual POR circuit is much more complicated than the simplified version shown. The POR circuit requires a startup module to generate a boot pulse. In this case, a monotonic power supply must be used (monotonically rising or dropping without oscillating power), because if if Using a non-monocular power supply, the non-monotonic slope may cause problems when the deviation is close to any threshold level.
Higher threshold deviations can cause the same non-monocular sequence to be valid for a certain component, but is invalid for other components, as shown.
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Non-monotonic power slope
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Monotonic power slope
Workaround: Use a monotonic power to avoid the problem of ramp.
Second, the system cannot start? May be residual
At some point, even if the power supply (disabled LDO) is disconnected, the energy storage capacitor will also retain a certain residual voltage, and the POR will not be reset correctly, and the device will not be initialized correctly. as the picture shows.
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Residual pressure
Workaround: This voltage should be as small as possible in order to ensure that residual pressure can fall below VT1.
Third, how to arrange it on power-on time?
Some data sheets give the recommended power supply "timing" that should be applied to devices with more than one power pin. Compliance with this sequence is very important. For example, think about a device with two independent power supplies.
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Recommended power-on time series
Workaround: Recommended Power Supply Sequence Requires Digital Power to power the analog power supply (this is routine because the digital module controls the analog module, so you must first supply power to the digital module), the module must first initialize. Which power is first started to rise, but the digital power supply must first span thresholds across analog power supply, as shown. If the delay between the power is about 100 μs, the effect should be small and the device should be initialized correctly.
Fourth, other summary
Due to internal triode parasitic effects, hundreds of MS slow power slopes may cause problems. The POR circuit is to be evaluated under various slew rates to ensure that it can work correctly under normal power conditions. The data manual explains whether a fast power ramp (100 μs or shorter) is required.
For example, for a circuit board that connects the power supply with a fine cable, the poor ground connection will have a high impedance, which may generate a burr during power generation. In addition, in some electromagnetic environments (EME), the parasitic gate capacitance of the MOS transistor may be charged, resulting in the transistor to operate normally unless the capacitor is discharged. This may cause POR initialization failure.
Drift and tolerances also need to be considered. In some cases, the discrete components such as capacitors have a high rate (up to 40%) and high drift (drifting with temperature, voltage and time). Further, the threshold voltage has a negative temperature coefficient. For example, VT1 is 0.8 V at room temperature, 0.9 V under -40 ° C, at +105 ° C to 0.7 V. , Reading the full text, the technology area
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