In the current transmission interface of DVB-C broadcast television system, there are two MPEG-2 video transmission interface standards: asynchronous serial interface standard ASI and synchronous parallel interface SPI. SPI has a total of 11 useful signals, and each signal is differentiated into two signals to improve transmission anti-interference. It is transmitted by DB25 on the physical link, so the connection is many and complicated, the transmission distance is short, and it is prone to failure. However, SPI is a parallel 11-bit signal with simple processing and strong scalability. Therefore, the output of the general MPEG-2 video encoder and the input of the video decoder are all standard parallel 11-bit signals. ASI uses serial transmission, which only needs a coaxial cable for transmission, which is simple to connect and has a long transmission distance. According to the advantages and disadvantages of SPI and ASI, it is necessary to convert between SPI and ASI of the transmission signal.
1 SPI signal structure
The parallel transmission system SPI includes a clock signal, an 8-bit data signal, a frame synchronization signal PSYNC and a data valid signal DVALID. The frame synchronization signal corresponds to the synchronization byte 047H of the TS packet. The DVALID signal is used to distinguish the length of the TS packet as 188 bytes or 204 bytes. When the TS packet length is 188 bytes, the DVALID signal is always high, and all signals are synchronized with the clock signal. The SPI data format is shown in the figure.
2 ASI interface
ASI transport stream can have different data rates, but the transmission rate is constant, 270Mbps, so ASI can send and receive MPEG-2 data at different rates. The ASI transmission system is a layered structure. The highest layer and the second layer use the MPEG-2 standard ISO/IEC 13818-(Systems), and the 0th and 1st layers are FC fiber channels based on ISO/IEO CD 14165-1. FC supports a variety of physical transmission media, this solution uses coaxial cable transmission.
First, convert the 8-bit codeword of the MPEG-2 transport packet that is synchronized with the packet into 10-bit codeword; then, in parallel/serial conversion, when a new word is required to be input and the data source is not yet ready, it should be inserted A K28.5 synchronization word to achieve ASI's fixed transmission rate of 270Mbps. The resulting serial bit stream will be sent to the coaxial cable connector through the buffer/drive circuit and coupling network. There are three ways to insert a synchronization code word: a single byte of the transmission code stream cannot be a synchronization word before and after; a single byte of a transmission code stream must be a synchronization word before and after; or a combination of the two.
The received data arriving at the coaxial cable must first be coupled to the circuit for recovering clock and data through the connector and coupling network, and then perform serial/parallel conversion; in order to recover byte synchronization, the ASI decoder must first search for K28.5 synchronization Word, once the synchronization word is searched, the boundary is demarcated for the subsequently received data, thereby establishing the correct byte arrangement of the decoder output bytes; finally, the 10/8-bit conversion is performed to restore the packet-synchronized MPEG-2 TS code stream data. But the K28.5 sync word is not valid data, so it must be deleted during decoding.
3 ASI interface implementation scheme
In this scheme, the MPEG-2 TS code stream is provided by the single-chip MPEG-2 encoder MB86390, which outputs a parallel 11-bit signal conforming to the SPI standard, and the TS packet length is 188 bytes. In the SPI/ASI conversion scheme, the cypress company cyb923/cyb933 chip, asynchronous FIFO and logic programmer CPLD are mainly used.
cyb923 mainly realizes the 8/10bit conversion of the codeword, inserts the synchronization word K28.5 and parallel/serial conversion. The transmission rate of ASI is constant at 270MHz, and the input MPEG-2 TS code rate is different, so to use FIFO to achieve rate matching, it is necessary to logically control the communication between the input SPI data, FIFO and cyb923. Considering comprehensive performance, price and program complexity, this solution uses xilinx's CPLD logic programmer XC95108; VHDL programming is used to realize their logic control. The decoding of ASI is also a similar process, cyb933 mainly realizes 10/8Bit conversion, removal of synchronization word K28.5 and serial-to-parallel conversion.
3.1 ASI encoding
In the ASI encoding process, only the eight-bit data of MPEG-2 TS and the one-bit TS transmission clock are input to the CPLD. Because in this scheme, the TS format is 188 bytes, the data valid signal DVALID is always high, and CPLD ignores this signal and only receives TS code stream data without caring about the synchronization header of the TS code stream. The PSYNC frame synchronization signal is also ignored. CPLD writes the received data into FIFO with TS code rate clock. When the FIFO is half full, the CPLD receives the half-full signal of the FIFO, and then the CPLD sends the FIFO read signal to the cyb923. The cyb923 reads the data in the FIFO at 27Mbps; when the CPLD counts to the cyb923 reads a certain amount of FIFO data, the CPLD Send FIFO unreadable signal to cyb923 to prevent FIFO from being empty. The maximum parallel speed of MPEG-2 transmission code rate is 27/8=3.375Mbps, and the read FIFO rate is 27Mbps, so the FIFO will not overflow. Taking into account the delay, this program uses a smaller capacity FIFO7202. cyb923 fills the ASI code stream with K28.5 when the FIFO is unreadable to maintain a fixed transmission rate of 270Mbps. Finally, the serial data can be transmitted by coaxial cable after being driven. In this solution, the insertion of the synchronization word K28.5 adopts the method of K28.5 synchronization words before and after a single byte of the transmission code stream. Compared with the other two schemes, this scheme is relatively simple to judge and deal with.
3.2 ASI decoding
At the receiving end of the ASI, the input ASI code stream is equalized and then input to the cyb933 chip. It first locks the ASI code stream clock by the internal clock phase-locked loop, and detects the synchronization word K28.5; after finding it, the ASI bit stream sequence is determined, and then serial/parallel conversion is performed.
It can be seen that K28.5 is detected, that is, byte alignment is an important prerequisite for ASI decoding, so cyb933 defines a set of methods for detecting byte synchronization. Considering that transmission errors and other reasons may cause false K28.5, cyb933 adopts the double-byte confirmation method. That is, the two consecutive bytes are both K28.5, and the byte synchronization is confirmed, and then the normal single-byte decoding state is entered. In the decoding state, if the CPLD counts 16 bytes out of the 64 decoded bytes to be wrong, the CPLD must send information to cyb933, requiring cyb933 to re-synchronize the bytes.
After byte synchronization, because K28.5 is the sync byte inserted by cyb923 and cannot be output as valid data, cyb933 automatically ignores these sync bytes. When cyb933 detects valid data, cyb933 will output an indication that the current data is valid. If this signal is regarded as valid for writing to the FIFO, the data in the FIFO must be valid data. When the FIFO is half full, after the CPLD receives the half full signal of the FIFO, the CPLD reads the data in the FIFO and determines the synchronization byte of the TS packet according to whether the read byte is 047H; if the synchronization word of the TS packet is found, it will Restore the corresponding frame synchronization signal. At this time, the CPLD count 188 restores the complete TS packet. If the next byte is not 047H, it means that the input data is incorrect. The CPLD will discard these data until it finds the 047H synchronization word. During this period, the CPLD outputs TS empty package. After re-packet synchronization, CPLD begins to count and output the correct 188-byte MPEG-2 TS packets, thereby recovering the correct 11-bit signal of SPI. Similarly, when FIFO data is unreadable, CPLD also outputs empty TS packets to maintain a constant output MPEG-2 code rate.
In the design of SPI to ASI conversion, ASI encoding is directly performed on SPI data without considering the problem of bit errors. The main consideration is that SPI data is directly output from MB390 without long-distance transmission, thus reducing the complexity of ASI encoding logic control. In the ASI decoding process, ASI data is transmitted over a long distance, and the error factor must be considered. Therefore, the resynchronization design of bytes and packets is added to increase the anti-interference ability. This scheme has realized the mutual conversion of SPI/ASI very well in practical application.
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