"Hello, we met again, Jaya brought or a FPGA board, this protagonist card is the advanced board card for the last Alinx Axu3eg development board, which is also an AXU4EV-P designed by Alinx. Development board. Let's take a quick book, let everyone look at the true face of Today's protagonist.
Now the ALINX's development board is basically playing the fashioned gold, and the courier package is opened. It is a inexplicable tall. It is still 2 boxes. This is consistent with the configuration of the AXU3EG development board. The size is larger.
Two boxes, a box is used to install the top of the board, which is a high black metal cartridge, and another box is used to install the related accessories, such as the downloader, power adapter, cable, and card reader.
If you have to say a black box, the protection of the board's body is still in place, and the entire circle is covered with foam, and the overall protection is in place.
The AXU4EV-P development board is still in the form of a sub-motherboard. It is compared to the AXU3EG development board. From the bottom plate, it can be said that it is full of more functions. Some children's shoes can be said that the core board of the two boards is exactly the same. Is it just the bottom plate function? Simple from the surface of the core plate, two is really exactly the same, but if you understand this core Zynq UltraScale chip, you may not think so, the core chips of the two cards are XCZU4EV and XCZU3EG, whether logic The unit is still functional, both new products have a certain difference. Let's introduce Zynq this magical series.
First, Xilinx has so many different FPGA series, Virtex7, Kintex7, Artix7, Spartan7 four FPGA series, why have you added an extra Zynq series? What is ZynQ and traditional FPGAs?
In fact, when we open Xilinx's official website, it will be understood that Xilinx has not calculated the Zynq series into FPGA at all, but is calculated as an SOC. In fact, SOC is more reasonable, editable logic gate, only one part of the system, compared classic FPGA, the largest feature of the ZynQ series is to separate the processing system PS and programmable resources PL, cured the presence of the PS system. , Achieved the true SOC (System on Chip). ZynQ's first generation of products, is the Zynq-7000 series, equipped with dual-core ARM CORTEX-A9 processors, A9 processors and programmable logic integration based on 28nm ArtIX-7 or Kintex®-7, achieve excellent performance power consumption And maximum design flexibility. The model and selection of the Zynq-7000 series can be understood by the following figure.
The Zynq-7000 series has gains a lot of success and innovation, familiar with children's shoes that are familiar with electronic technology, CPU or ARM core, and the method of implementing two devices in FPGA is completely different, so applicable functions are completely different, and the CPU can perform sequential execution Task, and FPGA is more good at parallel tasks. Under true application scenarios, it is often necessary to build a soft core in the FPGA, which will consume a lot of resources, and universality and portability will not be good, so we will see it. STM32 + FPGA, MINI PC + FPGA, and the like. The emergence of Zynq breaks the routine structure of this system structure, built a standard ARM core, and can complete the needs of most order tasks. It is also because of the pain points of Zynq solved, successful innovation will develop the Zynq UltraScale + MPSoc EV EV EV of the Axu4 EV-P development board.
After the Zynq-7000 line, the Xilinx Zynq series is constantly developing, as shown below, we can see that our protagonist AXU4EV-P development board is high-end Zynq UltraScale + MPSoc EV series chip.
Compare the difference between the chip of Zynq U1traScale + MPSOC we have in contact. The first is the difference in the PL side:
Zu3eg Device: 154K system logic unit, 7.6MB of memory, and 360 DSP SLICE.
ZU4EV device: 192K system logic unit, 18.5MB of memory, and 728 DSP SLICEs, comparison zu3eg will come out of a video code unit, this is the main difference between EV series and EG series, Video CODEC, video coding can be made .264 / h.265 encoding.
Based on the above data, we can easily understand the difference between two Zynq. The first largest difference is the logical unit. Zu4ev is more than 48K logic than ZU3EG. The more logic units, the more complex, then the logic can be built. Secondary memory, Zu4ev is more than 10.9MB more than zu3eg, double out, DSP is also doubled, two chips are relatively, Zu4ev will be more powerful to video processing, with built hardware Video Codec However, the H.264 / H.265 of the video can be coded, and the 1-way VCU, video code unit can help assist the VIDEO CODEC hard-core implementation.
I believe I have read the above-mentioned ZynQ series described above. For the entire development board already has a complete understanding, then the focus is on our development board, we still have learned from the core board.
A 5-piece Micron DDR4 chip is used on the Alinx AXU4EV-P core board. Model: MT40A512M16GE, single-chip capacity 1GB, where the PS is mounted 4-piece DDR4 (as shown below, red box), which consists of 64-bit data bus Bandwidth and 4GB capacity. The PL end is mounted (as shown below, yellow frame), which is 16-bit data bus width and 1GB capacity. The maximum running speed of the DDR4 SDRAM of the PS terminal can reach 1200MHz, which is the data rate of 2400Mbps. The maximum running speed of the DDR4 SDRAM of the PL end can reach 1066MHz, and the data rate is 2132 Mbps.
In addition to the DDR section, there is also a storage-related chip on the core board, which integrates a 256Mbit size QSPI flash (such as the following figure, red box) and 8GB EMMC Flash chip from Magic (as shown below, yellow box), these two storage The chip can be used to start the storage configuration, and the system and file system, etc. As shown in the blue box, the PMIC (Power Management Module), the chip is TPS6508641RSKR from Ti (Texas Instrument Semiconductor). This chip is TI specifically to configure FPGA, and MPSOCS power supply power management module, which is very high, with 6 DCDC Buck output, and 4 LDO output, but also through the I2C interface, PMIC Part of real-time adjustment and monitoring.
Then we have to see the back of the Alinx Axu4 EV-P core board, the main thing is 4 connectors, as well as some decoupling capacitors, as shown below. The connector is used to connect the signal of the motherboard and the bottom plate. These interfaces mainly extend the USB 2.0 interface, Gigabit Ethernet interface, SD card interface, and other remaining MIO ports; 4 pairs of PS MGT high-speed transceiver interface; and Almost all IO ports HP There are 96 I / O, and 84 of HD I / O. The XCZU4EV chip is taken along line between the interfaces, even if the high speed signal can be maintained, it can maintain a high signal integrity.
The ALINX AXU4EV-P core board is only 80mm x 60mm, which can be used for customized development, small size, high integration core board design, which can meet most of the application scenarios, convenient secondary development, core board design It also passed the consolidation of signal integrity, and the integrity of power supply. Overall, the ALINX AXU4EV-P core board is used as Blue. The design of Demo and product prototypes can greatly improve the development efficiency, and the energy is used in the core of the upper layer function. Design and implementation.
Compared to the AXU3EG core board, there is still some differences on the AXU4EV-P core board, the PCB used by the two boards should be the same board, but the BOM of the upper part is different, on the version of the AXU4EV-P, U83 , U33, U36, and the U36 is the upper part, but the AXU3EG core board is not visible.
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The U33 & U34 is TPS74801DRCR, which has 1.5A, low input voltage (0.8V), which adjusts the power supply normally indication and enabling function, adjusts ultra-low pressure regulator, is a high performance LDO from Ti, plus U83 The TPS72018DR is also the LDO of Ti. The three devices are mainly used to share the gth or gty of XCzu4ev, provide analog power supply voltage for the analog power supply voltage and terminal circuit, which should be because of the AXU4EV-P development board. There is a fiber SFP interface and a PCIe gold finger, so the GTH transceiver is used, so the emulation power of the transceiver needs to provide a high-quality LDO separately, which is to use a separate high quality LDO to the transceiver. Mainly because the speed of the transceiver is very fast, the analog circuit is a bit deviation of the overall result, in order to obtain good results, and is not subject to other module parts, it is necessary to use separate, and power quality is better. LDO, another reference, you can watch the power supply section, Zu4ev's manual only gives 3% of the power error space, and it is also possible to see the transceiver part of the demand for power supply. This part of the transceiver should be said in detail, and it is estimated that there is no other thing today. Interested partners can refer to the Xilinx documentation, with its own enlightenment.
Https://www.xilinx.com/support/documentation/user_guides/ug476_7series_transcers.pdf
This is relatively well understood on the ALINX AXU4EV-P core board. This power supply should be in the stage of doing a board, specially made compatibility design, this PL_VCU_0V9 power supply is a specialized VIDEO CODEC to Zynq Zu4ev Part of use, zu3eg does not have a video codec section, of course, no need.
If you feel that the Alinx Axu4ev-P core board is not enough, Alinx has greatly given a stronger solution, and AXU5EV-P. The number of resources doubled again, and the kernel cluster increased by 10%.
Alinx AXU4EV-P core board introduces a paragraph here, look at the bottom plate portion of Alinx Axu4ev-P, compared to the bottom plate of Alinx Axu4ev-P, but it is more rich than Alinx Axu3eg:
ALINX AXU4EV-P development board design block diagram:
The ALINX AXU4EV-P development board is equipped with a PCIe X1 standard M.2 interface for connecting M.2's SSD solid state drive, with a communication speed of up to 6Gbps. Only the SSD hard drive is only supported by people who are led to the computer, M2 does not introduce, the DP display interface is also the same as that, up to 4K x 2k @ 30fps output.
The Alinx Axu4ev-p development board has four usb3.0 we are using usb3.0. This part of the USB implementation is a USB function through the USB PHY USB3320C chip, and then cooperate with 2 pairs of differential signal transceivers, add USB3.0 HUB implementation. The function of USB3.0, oral description is painful, directly viewing. The Si5332 is a multiplex clock chip from Silicon Labs, to provide a reference clock for FPGAs, and other modules.
Alinx AXU4EV-P development boards There are also two Ethernets, GPHY KSZ9031RNX connected via RGMII interface. To put it bluntly, it is our top is the most common and unseained interface - the network port. UART does not have to be introduced, and the serial port is converted into the Mini USB interface via Silicon Labs CP2102. The AXU4EV-P expansion board also includes a Micro type SD card interface to provide users to access the SD card memory, store the Boot program of the zu4ev chip, Linux operating system kernel, file system, and other user data files. Since the level of matching Alinx is designed and converted on the signal, Ti's TXS02612RTWR is used.
The Alinx AXU4EV-P expansion board has an HDMI portion of Alinx Axu3eg, which is used by the ADV7511, ADV7611 to implement HDMI's income and output, can support 1080P @ 60 Hz. There is also a MIPI interface to connect to the camera. The FPC connector of the MIPI interface 15pin is connected to the 2 Lane's data and 1 pair of clocks, and the level of the BANK65 is 1.2V. At the same time, the Alinx AXU4EV-P expansion board also has an expansion port of FMC LPC, which can be external Xilinx or all of our ALINX's various FMC modules (HDMI input / output modules, binocular modules, high speed AD modules, etc.). The FMC extension contains 36 pairs of differential IO signals, which are connected to IO of Zynq Bank65 & Bank66, respectively. (As shown below, red box)
Alinx AXU4On the EV-P expansion board, there are many high-speed interfaces that require the use of GTH transceivers, first of all, PCIe X2 gold fingers, you can implement data transfer of PCIe 3.0 while compatible with PCIe 2.0. With the GTH transceiver of Zynq Bank224, single-channel communication rate can be up to 8G bit bandwidth. Then the fiber interface, purchase the SFP optical module (1.25g, 2.5g, 10G optical module) inserted into these two fiber optic data communication. The 2nd fiber interface is connected to the 2nd RX / TX of the GTH transceiver of Zynq Bank224, each TX transmission and the RX receive data rate is as high as 12.5Gb / s.
In this way, the overall structure of the ALINX AXU4EV-P development board will have a number, the software part is a VITIS unified software platform, this platform is an integrated integration of Xilinx's large-scale software, which mainly includes:
1. Comprehensive kernel development kit, can seamlessly build accelerated applications.
2. Complete hardware accelerate open source libraries, optimized for the Xilinx hardware platform.
3. Insert the development environment in a specific area, which can be developed directly in a familiar higher level framework.
4. Constantly developing hardware accelerated partner libraries and pre-built application ecosystems.
Alinx is also very powerful to give SOP, namely standard job programs, or called User Guide. In short, there is a relatively simple explanation, follow the steps step by step, just have not used Xilinx VIS, just as a try to give children's shoes, but the overall difference should not be large, 2020 Start Xilinx to upgrade the IDE package into a new development software group, change the original DCSoc named VISI, including Vivado and HLS, and import new like AI, VIDOE, etc., special application function software.
The VITIS development environment will be built when it is last simple to use the Alinx Axu3EG development board. This time, it will be tried to try the stage of use.
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Simplely performing an example of reading and writing, using the bare plate program is not Linux, I directly find the corresponding projects provided by Alinx.
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This experiment is relatively simple, and it is simply desirable to pass FATFS, the SD card, or EMMC read and write, FATFS is a general file system module for implementing the FAT file system in a small embedded system. FATFS's writing follows ANSI C, so it does not rely on the hardware platform. The FATFS system provides a lot of API functions, and we only need to look at it, we are in use.
F_mount - Register / log out of a work area (Work Area)
f_open - Open / create a file
f_close - Close a file
f_read - read file
f_write - write files
Interested in seeing FATFS more deeper, you can see the following website, this site gives the instructions and examples of each API function.
http://elm-chan.org/fsw/ff/00index_e.html
Provides the EMMC and SD card test programs, the program process is registration workspace -> Check Status -> Check if the driver is ready, if there is no existence, if it does not exist, create -> Check if the directory file exists If there is, delete -> Write a file -> Read the file content.
Note that the BSP is to check the Xilffs library.
Workspace registration, file system check, if there is no file system, you need to create a file system, use the f_mkfs function, if it is SD0, the path is "0:", if it is SD1, the path is "1:", create a file system For a longer time, you need to wait, then determine if the file exists, if you exist, remove it first, then write one file, and read it again. The code of operation is as follows
Here, you need to define file paths, file content, file path to note, if SD0 is "0: /", if SD1 is "1: /", for our board and now, SD0 is EMMC, SD1 is an SD card.
Download the EMMC program to the development board, then you will print the following information. If you already exist in the EMMC, the first statement is printed, and the last statement is the content in the print file. If it is an SD card, there will be the same log generation, but we can pull the card to observe on the computer.
This way, we follow the routine, realize the experiment of the bare board's FATFS read and write SD card or EMMC, and there are SOP and reference tutorials to achieve a relatively simple and convenient. Then I will find the compiled Petalinux system, I finally found the relevant image in the information, just this should be the binary file, did not pack, we want to burn or a little bit trouble, You need to burn the file in different address intervals of the SD card according to the address. Take a pass, I think we still choose to start with the SD card of us with Alinx. Go back to recompile.
Use Alinx to provide our Mini USB to USB YTPEA line to connect our computer's USB port and board's PS UART. Open the serial port by software, serial port COM14 (this different computer port number will be different, you can view it in device manager), serial port levy 115200.
Then we log in to the system of the ALINX AXU4EV-P development board PS side: User name: root, password: root. View the parameters of the CPU:
The system uses the Xilinx home's own Petalinux. Relatively speaking, we want to install some tools in this system, you need to perform cross-compilation, compile the software into the system. This is generally involved in the participation of Linux systems.
Alinx AXU4EV-P development board PS end CPU parameters, only 4 CPUs display, but I am curious, how should the two trial kernels of Cortex R5 should be used, but also study it.
When the ALINX AXU4EV is running, the system is basically in the IDEL state, the power consumption of the entire board is about 13.57W, and the 11.78W of the ALINX AXU3EG before we have nearly 2W, in fact, the main overhead It is a functional chip on the bottom plate, and the overhead of larger logic and memory within Zynq. Overall is still very considerable.
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