"Hello, we meet again. In this issue, Jaya brings an alinx Designed axu3eg development board. Xilinx is used Compared with its predecessor Xilinx zynq-7000 SOC series, the chip of zynq ultrascale + mpsocs eg series has stronger performance. Zynq MPSoC (multiprocessor system on chip) is the second generation SOC series products launched by Xilinx company. It integrates complex processing systems, including arm cortex-a53 application processor, arm cortex-r5 real-time processor and FPGA programmable logic.
For zynq, it is actually two functional modules, the PS (processing system) part and the SOC part of arm, which are independent of FPGA. The other block is the pl (progammable logic) part, which is the part of FPGA. Among them, PS integrates APU arm cortex ™- A53 processor, RPU cortex-r5 processor, AMBA ® Interconnection, internal memory (OCM), external memory interface (DDR controller) and peripheral (IOU). These peripherals (IOU) mainly include USB bus interface, Ethernet interface, SD / EMMC interface, I2C bus interface, can bus interface, UART interface, GPIO, etc. High speed interfaces such as PCIe, SATA and display port.
The entire alinx axu3eg development board is still a sub motherboard. One and the new version are matched with one motherboard. Acu3eg is the model of the core board. The zynq chip used for the main chip is based on xczu3eg-1sfvc784i of zynq ultrascale + mpsocs eg series of Xilinx company. In the part of the core board, five micro DDR4 chips mt40a512m16ge are used, in which four DDR4 chips (as shown in the following figure, red area) are mounted on the PS end to form a 64 bit data bus bandwidth and 4GB capacity. One piece is mounted on the PL end (as shown in the yellow area in the figure below), which is 16 bit data bus width and 1GB capacity. The maximum operating speed of DDR4 SDRAM at PS end can reach 1200MHz and the data rate is 2400mbps. The maximum operating speed of DDR4 SDRAM at PL end can reach 1066MHz and the data rate is 2132mbps.
In addition to the DDR part, there are memory related chips on the core board, which integrate a 256Mbit QSPI flash (as shown in the figure below, red box) and an 8GB EMMC flash chip from micron (as shown in the figure below, yellow box). Both memory chips can be used for startup storage configuration, system and file system. As shown in the figure below, the blue box is PMIC (power management module), and the chip is tps6508641rskr from Ti (Texas Instruments Semiconductor). This chip is a multi-channel power management module specially used by Ti to configure FPGA and mpsocs. The integration of this chip is really high. It has 6 DCDC buck outputs and 4 LDO outputs. At the same time, it can also adjust and monitor the PMIC part in real time through I2C interface.
For details of PMIC tps6508641rskr, please refer to the circuit diagram in the figure below.
Only the main devices on the front of the core board are left, and the largest zynq ultrascale + mpsocs eg chip has not been introduced. First, look at PS. compared with the previous generation, the biggest change of zynq's products is the change of PS end, as shown in the figure below.
The upgrade from the original zynq 7000 series SOC chip to zynq ultrascale + mpsocs eg series is mainly from single core / dual core arm cortex-a9 Mpcore ™( Up to 1GHz), upgrade to dual core / quad core arm cortex-a53 Mpcore (up to 1.5GHz). There are also dual core arm cortex-r5 mpcores famous for real-time performance ™。 It also adds a multimedia processing unit, that is, GPU, GPU arm Mali ™- 400 MP2 reaches 667mhz. Video encoder is also added to EV series devices, supporting h.264-h.265. Only the alinx axu3eg development board we use uses the eg series, so there is no video related encoder. However, the processing capacity in the video part is also greatly strengthened. If it is rfsoc, it will also include some characteristics of RF part and integrate ADC / DAC.
Compared with the zynq 7000 series, the zynq ultrascale + mpsocs eg series chips used in alinx axu3eg development board have no essential changes in the PL part, with more indicating logic, larger memory and more perfect computing units. Compared with the packages used, the real parts are sealed differently, and the number of corresponding logic units and storage units are different. Refer to the following table for detailed parameters:
The structural block diagram of zynq ultrascale + mpsocs eg series chips used in alinx axu3eg development board is shown in the figure below:
Then there is the back of the board, mainly the arrangement of four connectors and some decoupling capacitors, as shown in the figure below. The connector is used to connect the signals of the main board and the backplane. The insertion direction can be determined by a white arrow on the core board and the backplane. These interfaces mainly expand the USB2.0 interface of PS end, Gigabit Ethernet interface, SD card interface and other remaining Mio interfaces; Four pairs of PS Mgt high-speed transceiver interfaces are also extended; As well as almost all IO ports on the PL side, there are 96 HP I / OS and 84 HD I / OS. The routing from xczu3eg chip to the interface has been processed with equal length and difference, and the core board size is only 80mm x 60mm, which can be used for customized development. The core board design with small size and high integration can meet most application scenarios and facilitate secondary development.
Alinx pays great attention to the pin allocation of the interface corresponding to the core board, and most functions are pulled out of the interface.
Jaya, the core board of alinx axu3eg, is introduced here. Let's look at the expansion board. To be honest, the expansion board of this board card is really not like an FPGA expansion board. There are four USB3.0 interfaces, and the next door is the network port, which really brings Jaya into the raspberry pie in an instant. On the whole, the FPGA board is really like the backplane of a single board computer. I don't point out the functions one by one in the figure. They are all familiar common interfaces with strong scalability. At the same time, they can also be very convenient for the development and construction of prototype design.
1-way m.2 interface: it can be used to connect SSD SSD. The interface uses M key slot and only supports pci-e.
1-channel DP output interface: it is a 1-channel standard DisplayPort output display interface for video image display.
4-way USB3.0 interface: the USB3.0 host interface is connected through pipe3 interface and uses usb3320c chip to realize high-speed data communication between USB3.0 and USB2.0.
2-way Gigabit Ethernet interface: there are 2-way Gigabit Ethernet interfaces on axu3eg expansion board, one is connected to PS terminal and the other is connected to pl terminal. Gphy uses ksz9031rnx Ethernet PHY chip from Micrel to provide network services.
2-way USB UART interface: the two-way UART interfaces are also connected to PS end and PL end respectively. Use silicon labs cp2102gm chip to convert UART to USB.
1-way micro SD card holder: SD card is mainly used to store boot program of zu3eg chip, Linux operating system kernel, file system and other user data files.
1-way Mipi camera interface: the board contains a Mipi camera interface, which can be used to connect alinx Mipi ov5640 camera module.
Two 40 pin expansion ports: two 40 pin expansion ports J45 and J46 with standard spacing of 2.54mm are reserved on the axu3eg expansion board to connect various modules of alinx or external circuits designed by users.
2-way can communication interface; Two 485 communication interfaces: these four interfaces provide the board with the function of can & 485 communication.
1-way JTAG debugging port: used to download zynq ultrascale + program or curing program to flash.
1-way temperature sensor, 3 keys, 3 LED lights, 1-way EEPROM: some basic peripherals.
1-way RTC real-time clock: zu3eg chip has the function of RTC real-time clock, including month, day, hour, minute and second and week timing. Only a 32.768KHz passive clock needs to be connected externally.
At the end of the hardware part, the whole family photo of the kit: (axu3eg board body, 12V & 3A adapter, USB cable Downloader, 16g SD card, card reader)
The introduction of hardware has come to an end. Let's take a brief look at the software and application. Unfortunately, Jaya cleaned up the computer and reinstalled the system some time ago. Vivado has been completely emptied. If you want to realize the idea of simple try, Jaya can only reinstall it. It's just right. Xilinx provides a new tool set for zynq ultrascale + mpsocs eg series SOC, Vitis ™， Vitis unified software platform includes,
1. A comprehensive kernel development kit can seamlessly build accelerated applications.
2. The complete hardware acceleration open source library is optimized for Xilinx hardware platform.
3. Insert the development environment in a specific field, and you can develop directly in a familiar higher-level framework.
4. Evolving hardware accelerates partner libraries and pre built application ecosystems.
ALINX also gave SOP the awesome power. The so-called SOP is Standard Operating Procedure, that is, standard operation procedure, or User Guide. In short, with the relevant instructions, it's easier to install it step by step. Xilinx Vitis has not been used, and it's just a try for children's shoes. However, the overall difference should not be great. Xilinx has packaged and upgraded the IDE into a new development software group since 2020, changing the original dcsoc to Vitis, including vivado and HLS, And import new special application software such as AI, vidoe, etc.
OK, in that case, install it. The first thing is to install the package. This is still a little painful. Although Xilinx tools are fast, they can't support the whole software package. It's too big. Overall, 30 G. After a hard night of waiting, I finally got it.
In order to avoid detours, resulting in incompatibility and other wonderful problems, Jaya directly followed alinx's great steps to build the whole zynq environment into an environment consistent with alinx, so as to minimize variables.
As long as you operate step by step according to the manual, there is basically no difficulty in building the environment. Reference document: Course_ s0_ Xilinx development environment installation tutorial.pdf
The new environment is installed, but the overall difference is not big. Maybe Jaya hasn't used the different parts, such as AI, and then vivado or that vivado. Use it to experience the details.
OK, our protagonist who has been neglected for so long, let's set up our development board. First, there is an appearance image in the data provided by the development board, which is an image containing production test.
We use the etcher tool to burn this bin file into our SD card.
Next, we will switch the working mode of the board to SD startup.
After carefully looking through the manual provided by alinx, I found this one: axu3eg boot detection.pdf, which is quite conscientious. In that case, we will refer to this manual to go through the self-test process first to confirm that our FPGA is OK.
Find a display with DP and connect it with DP line after it is soft. At this time, we can see the following pattern on the display（ PS: the fan equipped with alinx is really loud. If it's still a little noisy around, there's no doubt about the heat dissipation effect)
After confirming that the display part is OK, we can access the mouse. For the peripherals, we can refer to the description in the manual. Since most functions are PS and PL, many test methods are loopback. The advantage of loopback is to test yourself. If the local loopback is successful, it shows that both interfaces are good.
Finally, we insert nvme's SSD and Mipi's CMOS sensor module to test the SSD and Mipi signals. Then we connect to the serial port of PS terminal to view the system information.
Login to the system: user name: root, password: root. View the following CPU parameters:
The system uses Xilinx's own petalinux. Relatively speaking, if we want to install some tools in this system, we need to cross compile the software into the system.
When the whole alinx axu3eg runs, the power consumption is slightly higher for other raspberry pies, rk3399 or other common embedded development boards
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