introduction
H. 264 Standard as a new generation of video coding standards, is a video coding standard for multi-bit rate, also known as JVT / AVC standards, which can be used for high-size HDTV and digital storage systems, and can also be used for low yield real-time communication systems. In the same image quality, h. 264 ratio H. 263 and MPEG a 4 can save 20% to 50% of the bit rate. For its basic grade, the complexity of the encoder is H. 10 times the 263. H. 264 Good network affinity and excellent compression performance make it a preferred choice for video applications, but its huge operation is a bottleneck of many applications. A low yard ratio real-time application encoding system is designed based on Niosii. The system takes full advantage of the parallel design structure of FPGA, using H. high compression ratio H. 264 Standard Coding, which can meet the requirements of low rate real-time coding.
1 H. 264 encoding system structure design
According to H. 264 / AVC encoder principle and structure, while taking into account the restrictions of existing hardware resources and the application requirements of the design, the H. shown in Figure 1 is designed. 264 / AVC encoding system structure.
The video image of the camera is first processed by the video acquisition module and stores the image data of the current frame into the SRAM. Then, in the macroblock MB (MAcRoblock), the original image is read from the SRAM, and the reference pixel in the reconstructed frame is read according to the position within the image frame of the MB, and the predicted macroblock and the current The macroblock pixel can be predicted. Next, the residual image is integrated with an integer DCT transform or a HAD-AMARD transform, and the transform output is quantified. The residual image of the quantitative output generates a reconstructed image for an interpretation of the reconstructed image as a reference on the one hand, and the entropy encoding process is obtained, and the entropy encoding process is obtained.
According to H. 264 / AVC standard, the entire encoding system is divided into several main parts of image acquisition, intra prediction, transformation, quantization, entropy coding, etc. The various modules are treated by the pipeline, and the efficiency of the hardware can be effectively improved.
2 Based on the H. of Cyclone II FPGA. 264 encoder implementation
The system uses SOPC design, mainly consisting of video acquisition modules, Niosii processor system. The use of Altera's DE2 development board is integrated into a SOPC system in a SOPC system. Where the Niosii processor system should assume image acquisition control, the image of the image. 264 Compressed coding work. In order to ensure the real time, the H. 264 After the software algorithm is running time, the custom module is used to H. 264 Encoder Key Algorithm for hardware acceleration.
2.1 Video Acquisition Module
Video acquisition is a video image processing, the premise of transmission, and the collected digital video images will directly affect the results of video processing. Figure 2 shows a video acquisition structure of an image processing system.
The ADI's multi-video decoding chip ADV7181B performs analog to digital conversion of the captured video images. The ADV7181B can automatically detect a baseband video signal such as NTSC, PAL, and SEC0M, and convert it to digital video signals based on 4: 2: 2 samples of 16/8-bit compatible CCIR601 / CCIR656 format; 6-way analog video input The port is input, and a single 27 MHz crystal clock input is employed; the user can configure the operating mode of the ADV7181B through the two-wire I2C interface.
When the system is powered on, the internal register of the ADV7181B is first configured using the I2C module. Since the camera output is an analog video signal of the PAL system, it is necessary to configure the ADV7181B to an analog video signal input, and convert it to a digital video signal in the CCIR656 format. The ADV7181B will convert the brightness signal, chroma signal (TD_DAT) of the active digital video image, and the field synchronization signal (TD_HS / VS) simultaneously input into the FPGA chip, extract the required digital image information through the image acquisition module, and will It is used to cache the image frame to be processed to the Alterade2 development board.
The design and implementation method of image acquisition module is described below.
According to the analysis of the hardware structure of the video capture, the structure block diagram shown in FIG. 3 is designed. It can be seen that the image acquisition module mainly includes images of image extraction, chrominance sampling rate transform, Y / CB / Cr image component separation, and image cache SRAM read and write control.
The image extraction submodule is in H. Under the control of the video acquisition control information of the 264 / AVC coding module, the required image data is extracted from the PAL digital video image of the ADV7181B. The actual image size of the camera is 768 × 576 pixels, where the base field and the even field are input. Since the image size of the system is 320 × 240 pixels, it is necessary to intercept the input digital video to meet the processing requirements of the system.
Considering that the difference between the top field and the bottom field in one frame is not large, only the two consecutive 320 neighboring pixel points of the middle 240 rows in the bottom is extracted, and 320 × 240 pixels is output. Video image data. The specific extraction process is shown in Figure 4.
H. The 264 / AVC supports processing of a cross-line or interlaced digital image of 4: 2: O format, so that the extracted digital image is required to perform chrominance sampling rate transformation. By simply averaged the chromatic image component of adjacent rods and even rows, the chromaticity sampling rate transformation from 4: 4: 4 to 4: 2: O, as shown in FIG.
The image data after the sampling rate is required to slide the area cache in the SRAM according to the Y / CB / Cr image type, to facilitate the encoding processing of subsequent H_264. Figure 6 shows the effect of the chromaticity component of the actual image in the sampling rate change.
2.2 H. 264 Encoder Core Module
Integrated existing factors such as hardware resources, real-time and realization difficulty, in the design, only intra prediction mode, encoders include intra prediction modules, transform quantization modules, and CAVLC entropy modules. When processed, intra prediction, conversion quantization and reverse reflection, and then perform CAVLC entropy encoding, then perform CAVLC entropy coding, and the bright color ratio of the image is Y: u: v = 4 : 2: o.
H. 264 Encoder design first with VC ++ in the PC, and later transplanted to the FPGA implementation with custom hardware module, the time required for both. It can be seen that h is implemented with hardware. 264 Compression encoding a frame image is only about 16 ms, which is greatly improved compared to the PC, and the hardware module occupies less than 50%, and the price is relatively high.
Since the custom intra predictive hardware module is higher than that of the software implementation is large, the key analysis of the intra predictive module hardware structure design.
According to H. 264 intra prediction algorithm, intra prediction module is designed in non-rate distortion optimization mode. It reads an MB (16 × 16) brightness and chrominance image data from the SDRAM, predicting and predicting mode selection, output predictive residual and optimal prediction in the brightness and chroma prediction module. Mode; at the same time, the predicted result is added to the residual value after the reverse DCT transform and the inverse quantization, and the SDRAM is written back after the reconstruction module compensates. The main structure is shown in Figure 7, and the entire module is divided into four sub-modules: interface module, brightness prediction, chrominance prediction, and image reconstruction modules.
4 RAMs are designed in the interface module for storing the original image and reference image data for prediction: RAM0 storage brightness prediction pixels, depth 32, address 0 ~ 15 storage upper prediction reference pixel, address 16 ~ 31 Store left predictive reference pixels; RAML stores the original value of the current macroblock, depth is 256; RAM2 storage chromaticity predictive reference pixel, depth 32, address 0 to 7 storage upper CB predictive reference pixel, address 8 ~ 15 storage left side The CB predicts the reference pixel, and the address 16 to 23 stores the upper side Cr predicts the reference pixel, and the address 24 to 31 stores the left Cr prediction reference pixel; RAM3 stores the current macroblock chromaticity original value, depth is 128.
The internal structure of the brightness prediction module is shown in Figure 8.
1 The mode selection module specifies the current macroblock according to the current macroblock, specifying the current macroblock to predict in a certain order, such as avail = "11" means that the upper and left side prediction reference pixels are available, then the current macroblock The order of DC, Hor, Vert, and Plane predicts. In the residual processing module, two prediction modes of the various prediction modes are saved in 2 RAM sequentials, so the cost function of the current prediction mode and the size of the previous prediction mode cost function are compared in the mode selection module. If the current prediction mode is small, the current prediction mode is better, and the predicted residual is specified in the last poor prediction mode when the next mode prediction is made. When the current macroblock is predicted, the mode selection module determines the optimal prediction mode according to each mode predictive cost function, indicating that the prediction mode corresponds to the RAM stored in the residual processing module, and the corresponding residual Enter the integer transformation module.
2 The prediction module contains four prediction modes of DC, Hor, Vert, and Plane, read the predicted reference pixel and the original pixel value from the interface module according to the prediction mode determined according to the mode selection module, and the post-residual output to the residual processing The module, the predicted value is output to the compensation reconstruction module.
3 Residual processing module uses two RAMs that store residuals, each macroblock can be used in parallel, and the residuals are saved to 2 RAMs, select the preferred prediction mode, and then do the next prediction mode. Compared to the preferred prediction mode selected until all prediction modes are selected to select the best prediction mode.
4 The predictive price module is the prediction price of each prediction mode. Take a Hadamard transform in 4 × 4 blocks. After the transformation, each 4 × 4 block DC coefficient is once again a Hadamard transform, and all transform results are absolute. Accumulation is the corresponding forecast price.
The chromaticity prediction module structure is basically the same as the brightness prediction, but since the chromaticity has both CB, Cr two components, the residual is slightly different in the RAM; the chromaticity prediction and brightness prediction of the same macroblock is executed in parallel Since the chroma data to be processed is half the brightness, the author uses the process of processing chroma in the back integer transformation, so that the water is more compact, reducing the waiting time, and improve the running speed of the entire module.
3 conclusions
Niosii-based low yard ratio real-time H. 264 Video encoding system, when the system clock frequency is 100 MHz, the color image of the compressed frame 320 × 240 needs 16.283 ms, when the quantization parameter is selected, the image compression ratio reaches 2%, real-time monitoring image frame rate 25 frames / S. The system has less resources, low cost, low yard ratio, high-definition video quality, has good development prospects.
Figure 9 is a resource occupancy of the system after integrated simulation in the integrated development environment.
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