"Oversampling technology is one of the methods often used by digital signal processors to improve the performance of analog-to-digital converter (ADC). It improves the signal-to-noise ratio of ADC by reducing quantization noise [1]. Oversampling technology not only does not add additional analog circuit, but also improves the effective resolution and simplifies the analog circuit, which is simple and easy. Therefore, it is widely used in the field of measurement and control by digital signal processing practitioners [2-6].
A key link of oversampling technology is the low pass filter (LPF) after sampling. Without this filter, oversampling can not produce any effect [7]. However, in many applications, a variety of signals need to be measured, and the data acquisition part must have adaptive characteristics, that is, the lower decimation rate can be selected independently according to the frequency band of the input signal, and the characteristics of the low-pass filter should also change after oversampling. Therefore, it is necessary to design a low-pass filter with variable parameters to meet this demand.
Low pass filter in oversampling Technology
The low-pass filter of oversampling technology should complete the functions of quantization noise filtering and anti aliasing filtering during downsampling at the same time. The filter parameters that the oversampling technology can perfectly achieve its goal meet: passband cut-off frequency, passband attenuation RC = - 3dB, stopband cut-off frequency, and stopband attenuation required to filter quantization noise is
Where, M is the oversampling rate, n is the down decimation rate, B is the original resolution of ADC, B0 is the improved resolution, n = 4B0, and usually there is. The type of filter is FIR filter, and its order is directly proportional to the down decimation rate.
Design of variable parameter low pass filter
It can be seen from section 2 that the filter characteristics in oversampling are determined by the resolution and down decimation rate of the ADC itself. When the decimation rate changes, the filter parameters will change, and the filter must be redesigned. From the design flow [8] of FIR filter, the filter coefficient will change with the change of cut-off frequency. If the filter coefficients are calculated after the cut-off frequency is obtained, it will bring a lot of computation, because IFFT (inverse Fourier transform) is performed for each group of filter coefficients. The usual way is to calculate the coefficient on the PC and make it into a look-up table. Due to the change of extraction rate, there will be many such tables, which will consume a lot of storage space. The method used in this section avoids this situation. Selecting a group of appropriate filter coefficients can complete the filtering of various lower decimation rates.
Filter coefficients determine filter characteristics. Theoretically, variable parameter filters can not be realized with only one set of filter coefficients. It can be seen from section 2 that the down decimation rate n is inversely proportional to the filter cut-off frequency, directly proportional to the stopband attenuation and directly proportional to the filter length. Assuming that the filter coefficients H (n), n = 0,1,2... L-1 when the decimation rate is N0, how can we obtain the filter coefficients when n is not equal to N0 through the set of reference coefficients H (n)?
When n
It is easy to achieve the lower decimation rate. However, at that time, the filter coefficient is greater than the reference coefficient. At this time, how to design the filter to meet the requirements? We use the interpolation FIR filter [8], which was originally used to realize the narrowband low-pass filter with high computational efficiency, to realize the change of low-pass filter parameters.
Based on the performance of L-TAP and non recursive linear FIR filter, the interpolation FIR filter is designed by replacing a single delay between the taps of the FIR filter of L-TAP with K unit delays. K is the expansion factor and an integer, as shown in Fig. 2. The original FIR filter is called prototype filter, and the filter with extended delay is called shaping sub filter.
The transfer function of the prototype FIR filter in the Z domain is:
In equation (3), LP is the length of HP. Then the transfer function of shaping sub filter is:
The extended impulse response length is
Figure 3 shows the effect of k = 3 unit delays in the frequency domain. The impulse response of the time domain filter is expanded by K times, resulting in the compression of the frequency domain amplitude response by K times, as shown in Fig. 3 (b). In the figure, those passbands centered on 1 / K integer multiples and repeated are called virtual images. As long as these virtual images are filtered out, a filter with constant attenuation characteristics and a cut-off frequency of 1 / K of the original filter can be obtained, which just conforms to the characteristics that the cut-off frequency of the low-pass filter after oversampling is inversely proportional to the down decimation rate, so it can be used in the design of variable parameter filter in oversampling. Here, the filter for filtering the virtual image is called the suppression virtual image filter.
Interpolation filter is actually a cascade of shaping sub filter and suppression virtual image filter. Shaping sub filter is well realized. As long as zero value is inserted as required on the basis of prototype filter coefficients, the following mainly focuses on the design of suppression virtual image filter. When the current decimation rate is greater than a certain value, the low-pass filter is a narrowband filter, and the virtual image of the shaping filter is also a narrowband. The amplitude response of the average filter is a narrow band notch at the integral multiple of 1 / L, which can filter out the virtual image generated by the shaping filter. The virtual image appears at an integral multiple of 1 / K. therefore, as long as the length of the average filter as the suppression virtual image filter is satisfied,
Figure 4 shows
The implementation process of interpolation filter in oversampling is as follows: after k-times interpolation of prototype filter, k-point average filtering can be done. It seems that it takes two steps to realize low-pass filtering. In fact, due to the characteristics of shaping and averaging filtering, we can complete the filtering in one step. According to equation (3), the output of the shaping sub filter is:
For the convenience of down decimation and calculation, the length of the shaping filter is changed from
It can be seen from equation (4-9) that the output of the interpolation filter is the result of averaging the k-point value and then weighted averaging with the prototype filter coefficients. It can be seen that the implementation method is very simple.
Implementation of oversampling technology in FGPA
Some general data acquisition modules need to realize the measurement of a variety of signals and pay attention to the universality of the module. Therefore, personalized things such as signal preprocessing circuits such as amplification and filtering are not allowed to exist. The oversampling technology is applied to the general module, the signal preprocessing circuit is omitted, the appropriate oversampling rate and down sampling rate are selected according to the signal characteristics, and the final sampling rate and resolution are balanced to obtain the required measurement accuracy. According to the requirements of the general module, the structure shown in Figure 5 is designed to realize the oversampling technology of the general module.
As can be seen from Figure 5, FPGA realizes the following functions: generating ADC timing and controlling ADC sampling frequency; Take the ADC conversion end flag bit as the trigger signal to read the ADC conversion data; In order to filter the quantization noise of ADC output signal and reduce the amount of data, low-pass filtering and sampling reduction module are realized; A ROM area is configured to store the filter coefficients for the implementation of the filter; To communicate with external processing engine, implement UART interface protocol; In order to make the modules work coordinately, a phase-locked loop is used to generate clocks with different frequencies.
The workflow of the module is as follows: the processing engine transmits the frequency of the signal to be measured to the low-pass filtering and de sampling module through UART, and the module sets the filter parameters and the down decimation rate of de sampling according to the frequency; The ADC timing module generates cnvst, starts the ADC for sampling, and the busy signal triggers the data reading module to read in the data; The low-pass filter and desampling module process the read data according to the set parameters and down decimation rate. After processing, the data is transmitted to the processing engine through UART for subsequent processing.
The ADC in the module is ad7674, 18 bit, 800ksps successive approximation analog-to-digital converter of ADI company, which has high data passing rate. It supports differential input mode, with adjustable load of internal sample and hold circuit and 5V single power supply. The device also integrates conversion clock, reference buffer and error calibration circuit, and has powerful serial and parallel ports, which are compatible with 3V and 5V levels. The FPGA selects Altera cyclone Ⅱ - EP2C8Q208C8, which includes five parts: programmable input / output unit, basic programmable logic unit, embedded block ram, rich wiring resources and underlying embedded functional unit.
Based on ad7674 and EP2C8, the relevant parameters obtained from the module design are:
(1) Lower extraction rate
(2) The resolution of ADC is 18 bits, and the maximum resolution after oversampling is 25 bits;
(3) The ADC reference voltage is 4.096V, and the resolvable signal size at the highest resolution is:
(4) In order to make the ADC reach 25 bit resolution, in addition to meeting the down decimation rate n = 47, it must also ensure that the stopband attenuation of the low-pass filter meets the requirements of oversampling. According to equations (1) and (2), stopband attenuation R0 = 64.3db. The Chebyshev best approximation method is used to obtain the filter coefficient. Through calculation and considering the design margin, it is obtained that when the filter length L = 4N and N = 47, the actual stopband attenuation is R0 = 75db; The filter coefficients are obtained by using the function chebwin (L, R0) in MATLAB software; The filter coefficients are quantized into 8 bits and decimated 16 times. The decimated value corresponds to the filter coefficients when n = 45. It is stored in the ROM area of FPGA, and the filter coefficients of other lower decimation rates are obtained based on this.
Experimental results and analysis
In order to investigate the correctness of the module design, it is tested. It is mainly divided into two parts. The first part is the test of low-pass filter. Firstly, take n = 1024 as an example to verify whether the amplitude characteristics of the actual filter are consistent with the design, and then verify the correctness of the design of variable parameter low-pass filter. The second part takes ECG signal as an example to verify the relationship between module resolution and oversampling rate.
Figure 6 shows the comparison between the filter amplitude characteristics designed by MATLAB and the measured filter amplitude characteristics when n = 1024. The test method is as follows: the sampling rate of ADC is 800KHz, the lower extraction rate is 1024, and the final sampling rate is; Add 3V sine waves with different frequencies to the system, and the frequency range is 5hz-360hz; The obtained data is transmitted to PC, and the FFT of each group of data is calculated with MATLAB to obtain the amplitude value; Assuming that the amplitude of 5Hz sine wave does not decay after passing through the system, the attenuation of each frequency point is calculated based on this. It can be seen from Figure 6 that the measured amplitude characteristics are basically consistent with the design. The disadvantage is that, limited by the sampling rate, the frequency of the measured signal cannot be greater than half of the sampling rate, and we can only get the attenuation of some sampling points.
Fig. 7 shows the amplitude characteristics of the variable parameter filter at different decimation rates. In order to verify whether the filter works normally when changing parameters, the input signals to the system are additive signals of 2V, 20Hz sine wave and 0.95v, 90hz sine wave. ADC samples the additive signals at the sampling rates of 12.5khz, 50KHz, 200kHz and 800KHz respectively. The lower extraction rates are 64, 256, 1024 and 4096 in turn, so the final sampling rate of the four groups of data is 195hz. Verify the attenuation of 90hz sine wave based on 20Hz sine wave. The black spots on each curve in Figure 7 correspond to the attenuation characteristics of 90hz, which are 15.345db, 15.504 dB, 15.54 dB and 14.958 DB respectively. Fig. 8 is a spectrum analysis of the signal after passing through the system. It can be seen from Fig. 8 that the 90hz sine wave is obviously suppressed, and its attenuation is 16.896 dB, 14.408 dB, 17.345 dB and 14.804 DB respectively. The measured data are basically consistent with the design, indicating that the filter under various parameters can work normally. In addition, the three small spikes in Fig. 8 are 50Hz interference and 20Hz harmonic respectively.
Figure 9 shows the ECG waveform of a classmate in the laboratory measured by the system. As can be seen from Fig. 9, with the increase of down extraction rate, the details of ECG signal become clearer and clearer, that is, the resolution becomes higher and higher. Therefore, with the increase of down extraction rate, the resolution of the system increases.
To sum up, the general data acquisition module based on oversampling technology can change its parameters according to the different measured signals to meet the measurement requirements. At the same time, it also completes the hardware implementation of variable parameter low-pass filter.
epilogue
In order to reduce the volume and cost of general data acquisition module, oversampling technology is applied to the ADC of the module. Because the general module measures a variety of signals, in order to meet the requirements of oversampling for low-pass filter, a variable parameter low-pass filter is designed. The filter is simple and computationally efficient. In the general module designed in this paper, each sampling point needs only 18 bits four times at most × Multiplication of 8bits.
In addition, the design of the module is implemented in hardware, and the module is tested. Finally, taking ECG as an example, the variability of parameters is verified., Read the full text, the original title: introduction and system design of low-pass filter in oversampling technology
Source: [micro signal: fpgaer]_ Club, WeChat official account: FPGAer club, welcome to add attention! Please indicate the source of the article“
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