"Overview
Whether a car is an auxiliary driving a car in the early 1920s, there is a car for smart subnet for an information entertainment system, a transmission system, and an autonomous driver assist system (ADAS), or the Level 3) And the above automatic driving cars (only the least human assist in driving in the traffic), the demand for the accelerated hardware acceleration in the traffic is rapidly increased. A few years ago, the most popular automotive intelligence model launched by NVIDIA, Mobileye and other CPU-centered suppliers, assume a centralized automotive network, in which a set of multi-core RISC CPUs with enhanced DSP functions A dedicated subnet. Now, the focus is rapidly turning to distributed automatic intelligence, including complex cameras with relevant visual systems, sensor subsystems with sensor central architecture from the Internet of Things, and for in-vehicle information entertainment systems (IVI) and ADAS The additional subnet, and the transmission system / powertrain network, together collaborate to achieve automatic driving functions.
Although Achronix expects future traditional vehicles and automatic driving vehicles to be distributed architectures, any network requires more reserve toggle more reserve more than currently realized architectures. The expected distributed computing architecture expected in the automotive network will be heterogeneous and need to be controlled from the network to a hybrid computing resource identified using the depth learning node. As a result, the current CPU of the luxury auxiliary driving is up to 100, and may increase to hundreds of CPUs in the automatic car. Sensor hub will require backup image processing to achieve distortion and splicing effect; Ethernet requires IP to packet filtering / monitoring, and special bridges with traditional CAN and FlexRay networks. Using integer CPUs and GPUs in the first generation car architecture, migrating to high professional computing nodes that require programmable acceleration.
In order to optimize chip area and power efficiency, integrated SpeedCoreTM embedded FPGA (EFPGA) silicon intellectual property (IP) into SOC compared to SOC or traditional FPGA, in a future car platform, to provide customers configurable Function is the best choice for realizing fast switching association. For more information on the evolution of the process, see Achronix White Paper (WP008): EFPGA acceleration in SOC - Understand the SpeedCore IP design process.
SpeedCore EFPGA IP's unique role in heterogeneous car data processing
The SpeedCore EFPGA IP can be integrated into the ASIC or SOC to provide customized programmable logical arrays. Customers specify their logic, memory, and DSP resource requirements, then Achronix configures SpeedCore IP to meet their specific needs. The SpeedCore lookup table (LUT), the RAM module, and the DSP64 module can be combined like building blocks to create the best programmable logical array for any given application. SpeedCore EFPGA IP provides unique advantages in automotive network integration, whether in existing design, replacing an FPGA or an ASIC.
l Higher performance - an EFPGA directly connects (no I / O buffer) to ASIC through a wide parallel interface, providing significant higher throughput, delay only the clock cycle of bit number. The delay is very important when you need a real-time response to a rapidly changing traffic conditions.
l Lower power consumption:
l The power consumption of programmable I / O circuit accounts for half of the total power consumption of independent FPGA. An EFPGA is directly connected to the SOC, completely eliminating large-scale programmable I / O buffers, thereby reducing power consumption.
l The area of an EFPGA can be accurately customized according to the requirements of the final application, and process technology can be adjusted to achieve performance and power consumption.
l Lower system costs:
l The core occupied area of EFPGA is much smaller than the equivalent independent FPGA, because the programmable I / O buffer, unused DSP and memory modules and excessive configured LUT and registers are all removed.
l With the SpeedCore custom module, custom functions can be added to the EFPGA logical array as an additional module and add them with traditional LUT, RAM, and DSP build modules. This efficient embodiment greatly reduces the size area of the core, minimizes power consumption, its overall result is greatly reduced system cost. For more details, see Achronix White Paper (WP009): Use the SpeedCore custom module to enhance the EFPGA function.
l Higher system reliability and yield - integrated the FPGA function into the ASIC, improve system-level signal integrity, and eliminate the reliability and yield loss of the installation of a separate FPGA on the PCB.
Treatment model centered on ADAS
Since the fusion of a plurality of visual processing systems is considered to be the core of driving assistance and automatic driving, the advanced driver assist system (ADAS) maintains a core position in the future car architecture, even if it is considered to be managers in the manager. The multi-core vision processor has also been partially replaced. The image relates to the image of the DSP and integer intensive tasks, which is initially considered to extract information from a static camera or video image to determine the object type, location, and speed. As designers are prepared for automatic driving vehicles, the role of the ADAS processor has extended to include visual, infrared, ultrasonic, laser radar (LIDAR) and radar images. In the conventional SOC and Association processor kit, the image pretreatment is performed separately from the CPU and must be connected to the CPU through one or more high speed bus. Even if the bus delay of the ADAS architecture is improved, the price of the delay is also paid when the coprocessor is implemented in a separate chip. Therefore, EFPGA IP is combined with the CPU in the unified ADAS architecture to ensure a fast response of visual, infrared or radar alerts in a rapidly changing traffic condition, which is the most effective way to verify.
Integrate multiple sensors from an ADAS kernel, providing an ideal application scenario in SPEEDCORE IP and a CPU parallel. SpeedCore IP supports customers to embed a customized programmable logic array into a standardized ASIC platform with dedicated computing resources (see the figure below). In practice, this integration can write data from the image source to the CPU cache, rather than writing a separate SDRAM. Reducing the interrupt of the CPU means having more real-time responses to objects in the vehicle field of movement.
Visual processors (usually from the 2D image from the camera, although more and more 3D images) can rely on graphics processors accumulated in edge extraction, format conversion, color balancing, and resolution for many years. Some processor IP vendors, including CEVA and Synopsys, also enhance the value of convolutional neural networks in object classification and identification. Representative as NVIDIA, experienced CPU vendors in these two areas, has tried to take balance between traditional CPU / GPU tasks and specific neural network mode identification engines. For the neural network sub-architecture in the automobile, it is moving from the early mature architecture that requires high precision floating point DSP to the self-training reasoning engine that can use the low-precision DSP kernel. The SpeedCore DSP64 module provides a lot of overhead for the new depth learning architecture. A common understanding of the evolution of ADAs and visual processing is that real-time car conditions will never have an optimal centralized ADAS processor or SOC. Always invisible collaborative processing and acceleration tasks are added to the central core of the ADAS.
The two additional functions inherent in any ADAS processor are sensor fusion / central integration and network conversion. The former involves combining information from various sensors: including CMOS images, infrared, laser radar and emerging sensors. Network conversion refers to the interface of the Ethernet's backbone network and CSI-2, FlexRay, CAN or even an earlier network protocol. Although the future ADAS SOC can indeed integrate a sensor center or an Ethernet MAC, there will always be some emerging functions, which is highly provided by the external logic outside the CPU. Since the sensor is aggregated and the network is interconnected in the chip before inputting to the CPU, it is a solution by reducing exposed interfaces, and the reliability is improved by the on-chip integration. For many such tasks, it will be Proof is the best solution.
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Figure 1: SpeedCore Array (left) link to the CPU subsystem and memory cluster
The role of programmable ability in functional security
The transition from driving auxiliary vehicles to a fully automatic driving vehicle has increased the status of safety in new cars. The more the network is more controlled by the vehicle, the more drivers expect multi-level safety to prevent such incidents such as 2016 Tsra death accidents that have attracted public attention. This driving force for fault-tolerant safety has prompted the industry to promulgate ISO 26262 standards for automatic driving vehicles, which are derivative standards for electrical and electronic systems IEC 61508 universal functional safety standards.
Early work in the EDA and SOC communities has implemented standardization of ISO 26262 method system to ensure functional security in IP. Fault Mode, Effect, and Diagnostic Analysis (FMEDA) technology describes the standard specification for IP unit functionality and fault mode, a fault pattern impact on product functions, automatic diagnosis of failure, design intensity, and operational diversity, including the environment pressure. A strong system should maximize the diagnostic coverage of the IP unit and provide height functionality by properly handling secure, detected and undetected failures.
The embedded FPGA can enhance the safety of the vehicle as the system due to its extremely programmable characteristics. In addition to the "sailing" function of the main control vehicle, the EFPGA in the SOC can also carry a large number of hardware diagnostic functions, and its running speed is more than a few quantities based on software-based diagnostics, which greatly increases any self-tail-over fault coverage. (BIST). In addition, they help automakers to update the deployed system in programmable, thereby helping the ISO 26262 security lifecycle. Take the Tesla car accident, if the root cause of the accident is an error in the object detection algorithm hosted in the hardware (due to performance reasons), it can be pushed to the entire team as long as the repair program is developed. You can bypass a long and expensive hardware development and re-deployment process.
Distributed control means distributed intelligence
Due to the installation of the camera and the demand for local sensor central, automotive designers are always planning to use a large amount of distributed intelligence in the vehicle body. Nevertheless, early supporters such as NVIDIA TEGRA, are considered to focus most of the intelligence in the dashboard or near, although it is a highly parallel CPU works in object recognition. Now, the fuzzy boundaries between the complete autonomy of the secondary ADAS in assist driving vehicles and the three-level self-driving cars have attracted people's attention, returning to distributed intelligence, where the CPU, GPU and neural network processors are provided in the body. Multiple management and control points. This transformation means more opportunities for programmable architecture exists outside the full covered SOC design.
Now, the ADAS processor market grows more than 25% a year. This growth is due to the function of automatic emergency braking, strain assist and adaptive cruise control, the ADAS function has been transferred from a luxury vehicle to a medium and entry-level vehicle - these features will be commonly used in the next decade. At the same time, the three-level automatic driving vehicle will be launched on a luxury platform such as BMW 17 in 2018, and the automatic five-level car may be available for commercial sales before 2022. As the autonomous driving platform develops from three levels to four and five, sensor hub, camera and laser radar / radar equipment will be spread throughout the vehicle, and each requires local control.
This control mode is clearly visible in the industry industry, such as Qualcomm Company's acquisition of NXP, and Intel's acquisition of Mobileye, the processor field will be directed to large suppliers of development ecosystems to specific professional fields. Taking the dominant status - Intel adopts server plus machine learning mode, Ying Weida adopts GPU / machine learning mode, Qualcomm uses a mode of cellular mobile communication, increasing the NXP Cognivue and I.MX processor. IP developers such as CEVA, Cadence / Tensilica, Synopsys / ARC, and Verisilicon will try to subvert the closed mode through their expertise in special processor kernels. At the same time, network experts such as Broadcom, Valens and Marvell will seek the car architecture around Ethernet main network.
Such a market pattern is similar to the era of enterprise networks into data centers. Semiconductor suppliers centered on processors try to define a complete system architecture, but the design area shows a diverse Wild-West style, which uses different logical kits to provide a component supplier (and OEM or automakers) Provide samples to create unique advantages. In such an environment, programmable logic configured for IP (such as Achronix SpeedCore EFPGA) will play an important role, not only in the near-term auxiliary driving and automatic driving development, but also in these two types of vehicles for many years. The same is true for distributed processor development.
SpeedCore EFPGA IP provides other advantages, such as by writing CPU caching instead of the film, not minimizing CPU interrupts. The BIST circuitry required in the CAN design typically accounts for 10% to 15% of the total ASIC circuit. Since the circuit supporting BIST can be programmed within EFPGA, these circuits can be omitted in many cases. In addition, EFPGA can provide diagnostics on the on-chip detection function. For existing ASIC-based, the flexibility of SPEEDCORE IP will support the new algorithm to program the new algorithm to program the new algorithm to extend the service life of the ASICs that have been deployed on site. Using SpeedCore IP in a 5G cellular network, using SpeedCore IP will also make the architecture a ideal choice for future V2X communication interfaces.In the future, automatic and advanced auxiliary driving vehicles, there are dozens of or even hundreds of distributed CPUs. The peripheral processing functions for connecting the car can be served by the ASIC, SOC or traditional FPGA. However, the introduction of SpeedCore EFPGA IP provides advantages of traditional FPGAs, delay, security, bandwidth, and reliability.
Original address: https://www.eeboard.com/news/speedcore-efpga/
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