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Suitable for board models:
PGL22G
1 Introduction
This tutorial describes how to use FTDI's FT232H drive chip to perform USB data transmission, and the underlying FPGA, the drive layer firmware (FT232H firmware) and the upper machine test software design are set forth to the entire process of USB development.
2. Experimental Principle
2.1 FT232H principle introduction
FT232H is a single-driven USB 2.0 drive chip produced by FTDI, USB speed up to 480MB / s, supports UART or FIFO mode, and can be configured into a variety of industrial serial or parallel interfaces:
(1) It is configured as a UART interface;
(2) FT245 synchronous FIFO interface;
(3) FT245 style asynchronous FIFO interface;
(4) Synchronous or asynchronous Bit-Bang interface;
(5) MPSSE interface;
(6) FAST serial port;
(7) CPU style FIFO interface;
(8) FT1248 interface.
The FT245 synchronous FIFO interface is configured in this experiment. Here is an internal structural diagram of FT232H.
2.2 Hardware Schematic
The USB section of the AX7035 / AX7050 development board is described below. The USB drive chip uses FT232HL, configured to ft245 FIFO mode, and configure the FT232 HL to configure the FT245 FIFO mode in the chip by connecting the 93LC56 memory chip.
AX7050 USB part Schematic AX7035 USB part schematic
2.3 FT245 FIFO interface pin
As shown in the following table, the ft245 FIFO interface is shown, and Adbus is a parallel interface for FPGA, and the RXF #, TXE # is an FT232H output signal for notifying the FPGA to be readable, RD #, WR # is read and write input signals, by FPGA control, CLKOUT is 60MHz, OE # is output, and it is necessary to at least one clock cycle in advance before RD # valid.
2.4 FT245 FIFO timing
The picture below shows the ft245 FIFO mode timing chart, in the read timing, first ft232h pulls the rxf # low, at this time, the data in the FIFO can be read, and the FPGA can pull the OE # first, at least one clock cycle, and then RD # Low, collected data in CLKOUT; in the timing, FT232h pulls the TXE # low, indicating that the FPGA can be pulled down, write data on the CLKout rising edge.
3. Program design
The program is relatively simple, and the function is implemented to store data read from the FT232H read FIFO to the double-port RAM, and then the data is read from the RAM to the FIFO of the FT232H, and the data is realized. The code implements its function according to the timing charts mentioned earlier.
A simple state machine is used in the code. First, it is first determined whether the FT_RxF_n signal is 0, if it is 0, enter the READ state, start reading the data of the FT232H, and stores in the RAM, if ft_rxf_n is high, enter the IDLE state Otherwise, it is determined whether ft_txe_n is 0 and the RAM space is not empty, enters the WRITE state, writes the RAM data to FT232H, if ft_txe_n is high or RAM empty, enter the IDLE state.
Pin name
Function description
FT_CLK
FT232H clock, CLKOUT frequency 60MHz
RST
Reset signal, high power is effective
FT_RXF_N
RXF # ft232h fifo can be read, low level is effective
ft_txe_n
TXE # ft232h FIFO can be written, low power is effective
ft_oe_n
OE # output enable, low power is effective
ft_rd_n
RD # read signal, low power is effective
FT_WR_N
WR # write signal, low power is effective
ft_data
FT232H data port, 8-bit bit wide, two-way IO
4. Experimental process
4.1 Installing FTDI D2XX Driver
In the 05_chip manual \ ft232h folder, you can find CDM V2.12.28 WHQL CERTIFIED_X64.ZIP to decompress it.
Take the development board, connect the USB interface of the development board, turn on the power
Open the device manager, appear new devices, right-click Update Driver Software
Click to browse your computer to find the driver software
Click Browse to find the unzipped folder, click OK, and click Next.
After successful installation, the driver is successfully installed as shown below:
You can see the USB Serial Converter device
4.2 Experimental Phenomenon
Download the program to the FPGA, find the hostile speed software, open the software
Select the USB device, click the start button
You can see that the read / write speed changes around 40Mb / s, click the pause button to stop speed.
Some students want to see the data transmitted by USB, here we offer "USB Test Tools", tools in the picture below:
The operation is as follows:
1) First ensure that the program (consistent with the speed measurement software) has been downloaded to the FPGA, connect the USB cable, find the upper machine speed software and open, find the USB device in the selection device drop-down box, if no USB device is displayed, click "Refresh" After the button is selected, click the "Open" button. As shown below:
2) Enter hexadecimal data in the data input box, then click Send, you can see the sending and reception data in the display window, perform data comparison, verify the correctness.
It is important to note here: Send data needs to be an even number, otherwise the upper chance intercepts several data transmission, as shown below, the last data f does not send it.
3) The "Refresh" button is similar to the closing port. After clicking the "Refresh" button, send data, there is no reaction, you need to click
The "Open" button opens the USB device.
5. Summary
This experiment introduces the read and write speed of the FT232H chip FT245 FIFO mode, you can combine the required functions required to write a host computer program. Read more
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