This paper analyzes the relationship between the growth of hydrogen etching time and defect density before growth. In fact, through the light-emitting and light analysis method, we found that the number of epitaxial defects and surface defects increased by the quantity of the surface defects increased. After increasing the hydrogen etching time, the substrate is changed, and the number of epitaxial layers defects increases.
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Silicon carbide (SiC) has good prospects in extreme conditions such as high-power, high temperature, high frequency. However, although the crystallization integrity of the commercial 4H-SiC single crystal circle has been significantly improved in recent years, the defect density of these wafers is still high. The study confirmed that the longer surface treatment time of the wafer substrate, the surface defect rate will also increase.
Be
Silicon carbide (SiC) has a wide range of band gap, high electric shock, high thermal conductivity, high carrier saturation rate, high-power, high temperature, high-frequency and other extreme conditions have good prospects . Although the crystallization integrity of commercial 4H-SiC single crystal wafer has been significantly improved in recent years, the defect density of these wafers is still high.
Be
The study confirmed that the longer surface treatment time of the wafer substrate, the surface defect rate will also increase. Surface defects have seriously affected SiC component quality than silicon, and the silicon carbide can be more wide, and the concentration of the gene is lower, and the semiconductor characteristics can be maintained under higher temperature conditions, and therefore, silicon carbide is used. The components made of materials can operate at a higher operating temperature than the components. The high thermal conductivity of silicon carbide is strong and high thermal conductivity, combined with high operating temperatures, allows silicon carbide components to achieve extremely high power density and energy efficiency.
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Today, the silicon carbide wafer quality and component manufacturing process have been significantly improved, and major semiconductor manufacturers have demonstrated high-pressure silicon carbide solutions, which are far exceeding the 萧特 二 diode (SBD) and field effect abductor ( FET), including blocking voltage close to a PIN tube; a slight-cutting voltage higher than 1.5 kV; breakdown voltage up to 1.0kV MOSFET.
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For ordinary semiconductor technology, especially silicon carbide components, the quality of substrate materials is extremely important. If there is a mechanical disorder area and an oxidation zone on the wafer non-uniform surface, the semiconductor element manufactured by these wafers will be affected, such as reorchase ratio, or unforeseen during normal operation. Performance reduces phenomenon. Commercial silica wafers require mechanical polishing treatment, the wafer surface is easily scratched, and there is a large number of scratches on the wafer.
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The past research report proves that if the surface of the substrate is properly treated before the epitaxial layer grows, the defects on the wafer substrate surface will be greatly reduced, which is the key to growing high quality epitaxial layers. We know that the hydrogen etching method can remove hundreds of body effect materials, thereby improving the defective problem of the wafer surface.
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S. Soubatch and other scientists studied the effects of hydrogen gas inversion method on zero-bias 4H-SiC (0001) wafer in a temperature range of 1,400 to 1,600 ° C. At high temperatures at 1,600 ° C, two different etching defects are more common, respectively, defects formed during step-by-step etching, and structural etching defects.
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The former contains large-scale and translucent bag height steps, which are typical in screw dislocation. The best surface morphology is a range of isometric levels, grown at 1,400 ° C.
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C. Hallin and other scientists studied the 4H-SiC and 6H-SiC substrate surface in situ preparation methods using hydrogen and hydroxane etching systems. The study found that the zero-zero surface after etching is more irregular, there is a large level zone and moisture pit, which may be higher in the defective zone; becomes large, and the microtubes and grain boundaries parallel to the surface are large, formation of triangular corrosion pits. The surface is perfiltrated with microtardries and other dislocations. However, we see a wider strip-shaped defect on the 4H hydrogen etching circle, namely the layers. Through increased propane in the hydrogen etching process, the best etching conditions can be obtained, and the scratches can be removed without leaving any tissue traces.
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The experiment studied the effect of hydrogen etching time on the surface of the substrate on the defect of the 4H-SiC epitaxial layer, and also studied the effect of etching time on the surface surface of the epitaxial layer with AFM analysis.
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Surface treatment time and defect rate are positive function relationship
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This paper utilizes a commercial low-pressure hot wall chemical vapor deposition (LP-CVD) reactor to expand the etch time three times to normal production time, and observe the effects of the study growth on the homogeneous epitaxial layer. After inspection and analysis, the relationship between etching time and defect rate is obvious. In addition, mercury probes CV and FT-IR measurement results prove that the doping and wafer thickness uniformity is also related to the etching time.
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This experiment uses the reactor to accompany the homogeneous epitaxial growth, and the SiH4 / C3H8 system is supplied to and carbon. Carrier gas and epitaxial growth reducing agent use high purity industrial grade hydrogen gas; add 10% of nitrogen gas to serve as a dopant. The reactor used in this experiment is the commercial low-pressure hot wall chemical vapor deposition reactor in Tokyo Powert. On the 4H-SiC (0001) silicon n-type (~ 1018AT / cm-3) substrate in the direction of the direction of 4 °, the N-SiC epitaxial layer of 1E16 AT / CM3 N-doped concentration is grown to avoid epitaxial layers. A rough mosaic pattern is formed.
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This experiment gates a 9.0 micrometer film epitaxial layer for medium and high pressure diodes or MOSFETs; manipulating changes due to etching time, with one-half reference etch time, reference etching time, twice-reference etch time and triple reference etch time The graduate process of its epitaxial layer; the doping concentration is 1e16 ATM / CM3.
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