H. 264 FPGA implementation of binary encoder
1 Introduction With the development of digital TV and video conference, H. 264 Highly compressed ratio, better image quality and good network adaptability are received. Adaptive binary arithmetic coding based on context is H. The last loop of the 264 encoder system has a greater impact on the entire encoding performance. CABAC fully considers the correlation between the video stream. Can adapt to changes in the statistical characteristics, easy to achieve progressive performance, high coding speed, large complexity, which is difficult to achieve high performance, especially for high-definition video (HDTV), can not realize real-time encoding This requires hardware acceleration or design a special hardware coding circuit. At present, there is a corresponding hardware acceleration circuit design, but mainly for the design of the arithmetic coding section, the overall performance is still not ideal. On the basis of the analysis of the previous acceleration circuit analysis, the CABAC is entirely encoded, mainly for optimizing the binary part, and optimizes the corresponding binary method, using parallel operation scheme, ultimately in FPGA Excellent speed and resource implementation of hardware coding.
2 binary principle CABAC implementation Program includes 3 processes: binaryization of syntax elements, context modeling, adaptive arithmetic coding, Figure 1 is the basic structure of the CABAC encoder.
Binaryization is the first step in CABAC encoding, and the encoding speed of the binary module helps to improve the entire system. During the binary process, a given non-two-in-kind syntax element is uniquely mapped to a bin string, each of which is called BIN. If you enter a given binary syntax element, this step can be crossed, and the subsequent step is determined by the encoding mode.
H. 264 standard. There are more syntax elements, with more than 20 kinds, and binary conversion makes the binary representation of these syntax elements to minimize redundant encoding to reduce streams. The binary conversion in Cabac has four basic types: one dollar (U) encoding, truncated one yuan (TU) encoding, index Columbus (EGK) encoding, and fixed length (FL) encoding. In addition, binary conversion can also be performed by series of coding modes. 2.1 yuan (U) binary conversion scheme For a symbolic syntax element X≥0, one dollar word in the CABAC is connected in series by X "1" and add "0" at the end, so one yuan binary The length is x + 1, as shown in Table 1, where binldx represents the index of the string. In general, U binary conversion is primarily used for reference frame queues to predict the encoding of syntax elements.
2.2 Truncate a dollar (TU) binary conversion scheme is truncated that the value of the grammatical element is required to carry out binding only for syntax elements that are not greater than a certain limit value (S). If the syntax element value is less than S, its binary results are binary binary; if the syntax element value is equal to S, the result is S "1". Typically, TU binary conversion is mainly used for encoding of intra-frame chromaticity prediction mode. 2.3 Index Columbus (EGK) Binary Conversion Scheme EGK Coding is initially proposed by Teuhola in the context control length coding scheme, which is derived from golomb. The EGK encoding is constructed in series by a prefix and the reclaimed code word, and its prefix portion consists of a value of a dollar code L (X) = [log2 (x / 2k + 1)], which is composed of X + 2K (1-2L (1-2L). x)) Calculate it. Generally, EGK binary conversion is mainly used for encoding of data outside of the residual, and the specific case of view encoder is set. EGK binaryization followed by different values, and K's value is non-negative integer. 2.4 Fixed Length (FL) Secondary Conversion Scheme Fixed Length Boundary Suitable for the case where the syntax element value X is smaller than the limit value S. The method is a binary representation of the X value as its binary results, and the length is similar to: LFL = [log2s]. In general, FL binary conversion is used to uniformly allocate syntax elements, and the graphic symbol part of the coding block is related to the luminance residual.
2.5 The substantially binary conversion series scheme can be derived from three basic binary conversion schemes by various binary conversion schemes. The first one is a 4-bit FL prefix with a series of Tu suffix (S = 2), while the second and third programs come from Tu and EGK binary conversion, referred to as UEGK. These programs are used in motion vector differential and transform coefficient to take absolute value. In addition, the syntax elements MB_TYPE and SUB_MB_TYPE binary use traversed binary tree, and the corresponding binary tree has been given in the reference.
3 binary coding scheme optimization H. The binary coding process in the 264 standard is serial, suitable for software implementation, but due to more grammatical elements, the execution speed is slow and the efficiency is low. The biggest advantage of hardware implementation is its consolidation, which can greatly improve the performance efficiency. Therefore, in order to improve the coding speed, the coding process in the standard is optimized accordingly in the premise that the algorithm is not changed, in order to facilitate hardware implementation. The following optimization measures are mainly proposed: (1) Classify the syntax elements in accordance with basic encoding methods and H. 264 For each grammatical element, 20 grammar elements can be returned to 6 types, including u binaryization, UEGKO binaryization (k = 0, UCO-EFF = 14), UEGK3 binary (k = 3, UCOEFF = 9), macroblock / submacca type binaryization, macroblock quantization offset binary, fixed length and truncation of binaryization. Classifying syntax elements will effectively reduce the complicacy and disorder in the encoding process, which is conducive to the normal completion of the encoding. (2) The binary method of parallelizing design syntax elements can be classified into 8, in the design, using the control unit to distinguish the corresponding syntax elements, and send the binary module for encoding. But according to H. 264 Standard design, the entrance address of the binary unit depends not only on the value of the grammatical element, but also depends on the type of grammatical element, which undoubtedly increases the amount of operation. And the output is serial, which is not conducive to the pipeline design, which will reduce the clock frequency of the system. Therefore, a parallel design is used, with the grammatical element value of the input, resulting in 6 different outputs, after latches them, using the multi-channel selector as the required value as the control terminal as the control end. Two different implementations are shown in Figure 2.
4 binary encoded FPGA implementation improved binary encoding mainly includes: control unit, binary coding unit, and selection output unit, as shown in Figure 3.
The circuit is mainly divided into 5 level flow water lines. In the first stage flow wire, the syntax elements (SE), clock signal (CLK), context model parameters (A, B) are input to the control unit. The control unit uses a comparator to determine the type of two-in-bubbles taken by the species signal (selector) output by comparing the type of the grammatical element to determine the type of the grammatical element.
Level 2 pipeline contains 6 modules, which represent six binary methods, respectively. Where u-coding, the MB_TYPE / SUB_MB_TYPE syntax element encoding module is easier to implement. Because the bit width of the input syntax element is 6 digits, the amount of data is not large, and the code table is made according to its encoding method, and this code table has a lot of resources, and the hardware implementation is implemented in RAM, and the speed is faster. For the implementation of the UEGK0 and UEGK3 encoding modules, the hardware mode of the combination of UE coding and EGK encoding is required, and the specific basic structure is shown in FIG.
In Fig. 4, first determined by the preparation unit, the current bit is encoded, in the EGK encoding, mainly adopted the first detection and bucket shift technology, and finally add two encodes to the output. For UEGK0 and UEGK3 encoding modules, simply select different thresholds. For the syntax element MB_QP_DELTA, the EGK encoding with positive and negative symbols is used, and the positive and negative number is determined by the odicle value of the syntax element. For the syntax element CODED_BLOCK_PATTERM, the encoding method combined with the TU is used. Because the amount of data of FL and TU encoding is not large, it is implemented in a surfactant, which can improve the speed, where FL encoding is 15, TU The boundary value of the encoding is 2. The main function of the third level flow line is to choose. Level 2 output includes an element (binary_value) and context model parameter (CTXOffset0, CTXOFF-SET), in level 3, by selecting the selection signal to select. The 4th-level flow wire is 32-bit advanced first out (FIFO) memory. The result is cached, which is conducive to the next level. Leading 5 is a serializer, mainly processed binary data, allowing it to output, and each bit of binary is added to its corresponding context model for subsequent processing. The output of the entire system is the binary data (SDA) and its offset (CTXIDXL).
5 Circuit Simulation and Performance Analysis This algorithm is Vc ++ simulation verification, which can be to H. The main grade video code stream in the 264 standard is encoded, and the result is H. The 264 standard program JM8.6 is the same. The circuit structure uses the Verilog language to perform RTL level description, and simulate mod-elsim6.0 software, the post simulation waveform is shown in Figure 5.
As can be seen from Fig. 5, in each cycle, in the case where the enable signal is valid, 1 BIT data SDA and the corresponding offset CTX-Idx1 can be generated to meet the design timing requirements. The circuit is integrated, layout, and uses Synplify, the highest clock frequency is 100 MHz, which affects the key path of the clock frequency is advanced first-output memory module. Enter a comprehensive EDIF circuit network file to the Foundation software of the backend FPGA vendor Xilinx to lay out, generate binary flow files, and the logic unit is 171, accounting for 4% of total resources. Use the design of the circuit to H. 264 Some standard video sequences in the standard are tested, the sequence quality is QP = 28, and H. The coding time comparison of the binary part in the standard program JM8.6, as shown in Table 2.
In summary, this article is H. The optimization of the 264 encoder binary part makes it a large increase in speed, and the resource usage is small. The hardware design of the binary part can not only complete H. 264 The basic grade code in the standard is also expected to be applied to real-time video compression coding of larger size.
6 Conclusion is in H. 264 Based on the study and analysis of the binary part of the standard, the FPGA circuit structure is proposed, and the parallel structure and pipeline design circuit are used. This structure is achieved by Spartan3 FPGA, which has a per-cycle 1 bit, the maximum clock frequency is 100 MHz, which can meet H. 264 The level 3 and its above the above-mentioned real-time video coding. Technology area
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