H. 264 Standard as a new generation of video coding standards, is a video coding standard for multi-bit rate, also known as JVT / AVC standards, which can be used for high-size HDTV and digital storage systems, and can also be used for low yield real-time communication systems. In the same image quality, h. 264 ratio H. 263 and MPEG a 4 can save 20% to 50% of the bit rate. For its basic grade, the complexity of the encoder is H. 10 times the 263. H. 264 Good network affinity and excellent compression performance make it a preferred choice for video applications, but its huge operation is a bottleneck of many applications. A low yard ratio real-time application encoding system is designed based on Niosii. The system takes full advantage of the parallel design structure of FPGA, using H. high compression ratio H. 264 Standard Coding, which can meet the requirements of low rate real-time coding.
1h. 264 encoding system structure design
According to H. 264 / AVC encoder principle and structure, while taking into account the restrictions of existing hardware resources and the application requirements of the design, the H. shown in Figure 1 is designed. 264 / AVC encoding system structure.
The video image of the camera is first processed by the video acquisition module and stores the image data of the current frame into the SRAM. Then, in the macroblock MB (MAcRoblock), the original image is read from the SRAM, and the reference pixel in the reconstructed frame is read according to the position within the image frame of the MB, and the predicted macroblock and the current The macroblock pixel can be predicted. Next, the residual image is integrated with an integer DCT transform or a HAD-AMARD transform, and the transform output is quantified. The residual image of the quantitative output generates a reconstructed image for an interpretation of the reconstructed image as a reference on the one hand, and the entropy encoding process is obtained, and the entropy encoding process is obtained.
According to H. 264 / AVC standard, the entire encoding system is divided into several main parts of image acquisition, intra prediction, transformation, quantization, entropy coding, etc. The various modules are treated by the pipeline, and the efficiency of the hardware can be effectively improved.
2 Based on the H. of Cyclone II FPGA. 264 encoder implementation
The system uses SOPC design, mainly consisting of video acquisition modules, Niosii processor system. The use of Altera's DE2 development board is integrated into a SOPC system in a SOPC system. Where the Niosii processor system should assume image acquisition control, the image of the image. 264 Compressed coding work. In order to ensure the real time, the H. 264 After the software algorithm is running time, the custom module is used to H. 264 Encoder Key Algorithm for hardware acceleration.
2.1 Video Acquisition Module
Video acquisition is a video image processing, the premise of transmission, and the collected digital video images will directly affect the results of video processing. Figure 2 shows a video acquisition structure of an image processing system.
The ADI's multi-video decoding chip ADV7181B performs analog to digital conversion of the captured video images. The ADV7181B can automatically detect a baseband video signal such as NTSC, PAL, and SEC0M, and convert it to digital video signals based on 4: 2: 2 samples of 16/8-bit compatible CCIR601 / CCIR656 format; 6-way analog video input The port is input, and a single 27 MHz crystal clock input is employed; the user can configure the operating mode of the ADV7181B through the two-wire I2C interface.
When the system is powered on, the internal register of the ADV7181B is first configured using the I2C module. Since the camera output is an analog video signal of the PAL system, it is necessary to configure the ADV7181B to an analog video signal input, and convert it to a digital video signal in the CCIR656 format. The ADV7181B will convert the brightness signal, chroma signal (TD_DAT) of the active digital video image, and the field synchronization signal (TD_HS / VS) simultaneously input into the FPGA chip, extract the required digital image information through the image acquisition module, and will It is used to cache the image frame to be processed to the Alterade2 development board.
The design and implementation method of image acquisition module is described below.
According to the analysis of the hardware structure of the video capture, the structure block diagram shown in FIG. 3 is designed. It can be seen that the image acquisition module mainly includes images of image extraction, chrominance sampling rate transform, Y / CB / Cr image component separation, and image cache SRAM read and write control.
The image extraction submodule is in H. Under the control of the video acquisition control information of the 264 / AVC coding module, the required image data is extracted from the PAL digital video image of the ADV7181B. The actual image size of the camera is 768 × 576 pixels, where the base field and the even field are input. Since the image size of the system is 320 × 240 pixels, it is necessary to intercept the input digital video to meet the processing requirements of the system.
Considering that the difference between the top field and the bottom field in one frame is not large, only the two consecutive 320 neighboring pixel points of the middle 240 rows in the bottom is extracted, and 320 × 240 pixels is output. Video image data. The specific extraction process is shown in Figure 4.
H. The 264 / AVC supports processing of a cross-line or interlaced digital image of 4: 2: O format, so that the extracted digital image is required to perform chrominance sampling rate transformation. By simply averaged the chromatic image component of adjacent rods and even rows, the chromaticity sampling rate transformation from 4: 4: 4 to 4: 2: O, as shown in FIG.
The image data after the sampling rate is required to slide the area cache in the SRAM according to the Y / CB / Cr image type, to facilitate the encoding processing of subsequent H_264. Figure 6 shows the effect of the chromaticity component of the actual image in the sampling rate change. Read more
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