"With the increasingly stringent power requirements, regulations, efficiency standards and EMI requirements, switching power devices are increasingly needed for power supply because of their higher efficiency and wider operating range. At the same time, designers continue to bear the pressure of reducing costs and saving space. In the face of these needs, they need to replace the classic silicon (SI) based MOSFET products.
Silicon carbide (SIC) is now mature and developed to the third generation, which has become a wise choice. SiC Based FET has many performance advantages, among which the most prominent characteristics are higher efficiency, better reliability, less thermal management problems and less space. These products are suitable for the whole power spectrum and do not need to completely change the design technology, but some adjustments may be required.
In this paper, Si and SiC are briefly compared and introduced Cree/Wolfspeed And illustrates how to use such devices for design.
Comparison between SiC and Si MOSFET
First of all, we should clearly understand the relevant technologies and terms: SiC Based FET is MOSFET, just like the previous silicon wafer. Broadly speaking, their internal physical structures are similar. They are three terminal devices with source, drain and gate connections.
The difference is as the name shows: SiC Based FET uses silicon carbide as the substrate, not just silicon. Many people in the industry call it SiC device, ignoring the MOSFET part. In this paper, it is called SiC FET.
Why use SiC compounds as materials? Due to various deep-seated physical reasons, SiC has three electrical characteristics, which are obviously different from silicon, and each characteristic gives it working advantages. In addition, there are other more subtle differences in SiC (Fig. 1).
Figure 1: approximate comparison of key material properties of SiC with Si and Gan solid materials. Compared with Si, SiC has higher critical breakdown voltage, higher thermal conductivity and wider band gap（ Image source: ResearchGATE)
These advantages include:
Higher critical breakdown electric field voltage (about 2.8 MV / cm, Si is 0.3 MV / cm), so when working at a given voltage rating, a thinner layer can be used to greatly reduce the on resistance.
Higher thermal conductivity, so higher current density can be achieved in the cross section.
A wider band gap (the energy difference between the top of the valence band and the bottom of the conduction band in Semiconductors (and insulators), in EV), makes the leakage current lower at high temperature. For this reason, SiC diodes and FETs are often referred to as broadband gap (WBG) devices.
As a result, the blocking voltage of SiC based devices is about 10 times higher than that of silicon devices, the switching speed is about 10 times that of silicon devices, and the on resistance at 25 ° C is only half or lower than that of silicon devices. At the same time, it can work at a temperature of up to 200 ° C (125 ° C for silicon devices), thus simplifying thermal design and thermal management.
The gate driver is critical to achieving this advantage
Without a gate driver, the power device cannot work. The gate driver converts the low-level digital control signals into the required current and voltage signals and provides the required timing for the power devices (while also providing some protection against most types of external faults). For SiC FET, the driver must have some additional functions to achieve the following purposes:
Minimize conduction loss, switching loss and gate loss. These losses include off and on energy, Miller effect, and gate drive current requirements. The off energy can be calculated according to the grid resistance and grid source voltage in the off state. In order to reduce these losses, more current must be drawn from the grid. One way is to have the driver apply a negative bias to the gate voltage during shutdown. Similarly, reducing the gate resistance can reduce the on energy consumption.
Minimize Miller effect and its negative impact; In some cases and application configurations, parasitic capacitance may cause accidental conduction. This conduction caused by Miller effect will increase the reverse recovery energy and increase the loss. One solution is to provide the driver with a so-called Miller clamp protection function to control the drive current during power stage switching.
Provide the required filling current and pulling current at an appropriate voltage. In order to minimize the loss, the positive bias gate drive (+ 20 V) required by SiC devices is generally higher than that of silicon-based MOSFET. SiC devices may also require a negative off gate voltage of - 2 to - 6 v. The required gate current is determined by routine calculation according to gate charge (QG), VDD, drain current ID, gate source voltage and gate resistance, and the typical value is about a few amperes. The current must have sufficient filling current and pulling current rating, and its voltage swing rate must be commensurate with the switching speed of SiC FET.
The parasitic effects (including stray inductance and capacitance) of circuit boards and devices are modeled and minimized to avoid oscillation, voltage / current overshoot and false triggering under the high switching speed of devices. Silicon MOSFET has a small "tail" current, which acts as a damper or buffer to reduce overshoot and transient oscillation to some extent. SiC MOSFET does not have this tail current, so the drain voltage overshoot and transient oscillation may be high and cause problems. To reduce these parasitic effects, we need to pay special attention to the circuit layout, shorten the wire length as far as possible, and place the driver as close to its power device as possible. Even a few centimeters long can be important because these stray inductances and capacitors are more significant when SiC FETs operate at higher switching speeds. Another advantage of reducing transient oscillation is that it can reduce the generation of EMI related to high-speed switches on the drive side and load side of the device.
Although there are other problems involved in driving SiC MOSFET, many suppliers have designed standard IC for this purpose, and its characteristics can meet the specific needs of SiC devices. Note that in many designs, the gate driver and SiC FET must be electrically isolated from the low voltage circuit. This can be achieved by optical, pulse transformer or capacitive isolation technology and using standard components. Firstly, isolation is for safety to prevent users from being infringed by high voltage in case of circuit failure. Secondly, MOSFETs in many circuit topologies (such as bridge configurations) are not grounded themselves, so they need to be isolated.
Performance and capabilities of new devices
Cree / wolfspeed launched the first commercially packaged SiC MOSEFT cmf20120d in January 2011 (wolfspeed is Cree's power and RF department, the name was announced in 2015), and SiC wafers were on the market a few years ago. The rated value is 1200 V / 98 a, the on resistance is 80 m Ω (all values at 25 ° C), and it is packaged in TO-247. After that, Cree soon launched the second generation Process, and now the third generation SiC MOSEFT is provided Specify the c3m device (Figure 2).
Figure 2: Cree's second generation (left) And third generation (right) sic The comparison of process structures shows little difference, but these profiles do not show the final performance specification improvement（ Image source: Cree / wolfspeed)
For example, c3m0280090j It is one of the first 900 V SiC MOSFET platforms in the industry. It is optimized for high-frequency power electronics applications, including renewable energy inverter, electric vehicle charging system and three-phase industrial power supply (Table 1).
In addition to the voltage / current specification, the device is also optimized for high-speed switching with low capacitance. It adopts low impedance package, has driver source connection (Fig. 3), includes a fast intrinsic diode with low reverse recovery charge (qrr), and has a wide creepage distance between drain and source (about 7 mm). Table 1: the excellent characteristics of c3m0280090j SiC MOSFET of Cree show that it is suitable for renewable energy inverter, electric vehicle charging system and three-phase industrial power supply（ Form source: Cree / wolfspeed)
Figure 3: c3m0280090j of Cree is packaged with low impedance and has driver source connection（ Image source: Cree / wolfspeed)
With this 900 V platform, a new generation of power conversion systems with smaller size and higher efficiency can be realized. Its cost is equivalent to that of silicon-based solutions, but its performance specifications are better. The safe working area (SOA) curve summarizes the capabilities of the SiC FET (Figure 4). When the drain source voltage (VDS) is low, the maximum current is limited by the on resistance; In medium VDS The device can maintain a current of 15 A in a short time.
Figure 4: Cree's c3m0280090j safe work area curve shows its IDs And VDS Ability（ Image source: Cree / wolfspeed)
Packaging affects performance
Cree also provides three devices with similar specifications - c3m0075120d and c3m0075120k and C3m0075120j, the difference is mainly caused by different packaging (Fig. 5).
Figure 5: Cree's 1200 V SiC FET has three packages with roughly similar specifications, but not exactly the same（ Image source: Cree / wolfspeed)
These numbers describe data, but the specific application is another matter. Devices with suffix D adopt three terminal package (to-247-3), while devices with suffix K adopt four terminal package (to-247-4). Both devices and the seven terminal device with suffix J have Kelvin source pins, which can reduce L in the gate circuit × Voltage spike effect caused by di / dt. In this way, a greater voltage can be applied to the grid and source, so as to achieve faster dynamic switching. When the device is measured near the rated current, the results show that the switching loss may be reduced by 3.5 times.
Evaluation board and reference design accelerated successfully
Although very different from the gigahertz RF design, building high-performance circuits to work in a higher voltage and power range still requires attention to detail. Every detail and feature of components and layout will be amplified, and the actual circuit will not forgive even the smallest problems and omissions.
To help designers evaluate SiC FETs such as c3m0075120d and c3m0075120k, Cree provides KIT-CRD-3DD12P Buck boost Evaluation Kit to demonstrate the high-speed switching performance of these devices. It supports both the three terminal package of c3m0075120d and the four terminal package of c3m0075120k (the same as the former in other aspects). Designers can test and compare the performance of Cree / wolfspeed third generation (c3m) MOSFETs in different packages.
The Evaluation Kit has a half bridge configuration that allows the addition of MOSFETs or diodes above and below, so the board can be configured as a common power conversion topology, such as synchronous buck or synchronous boost. It also allows the addition of diodes at the top or bottom, allowing the user to evaluate the asynchronous buck or asynchronous boost converter topology.
In addition, in order to reduce power loss, the kit is equipped with a low loss inductor made of "iron silicon aluminum magnetic powder". This magnetic metal powder, also known as Kool m µ, consists of 85% iron, 9% silicon and 6% aluminum. It improves the specifications of key magnetic and temperature parameters and can replace permalloy.
For users who need to design their own gate driver sub circuits, Cree / wolfspeed is also the third generation SiC FET provides CGD15SG00D2 Grid driver reference design (Figure 7).
Figure 7: top (left) and bottom (right) of cgd15sg00d2 gate driver reference design; This is a complete circuit board with complete BOM, which provides conditions for users to evaluate the performance of three pin and four pin TO-247 packages (using the same SiC MOSFET chip)（ Image source: Cree / wolfspeed)
The high-level block diagram (Figure 8) of cgd15sg00d2 shows the functions of the reference design, including optocoupler (U1), gate driver integrated circuit (U2), and isolated power supply (x1). The optocoupler (5000 V AC isolation) receives pulse width modulated (PWM) signals and provides common mode immunity of 35 / 50 kV / µ s (minimum / typical). Other notable features include:
A groove to enhance the forced creepage distance Specification between the logic side and the power side of the printed circuit, and there is a 9 mm creepage performance enhancement gap between the primary circuit and the secondary circuit of the circuit board.
A 2 W isolated power supply to support the operation of larger MOSFETs at higher frequencies.
Separate gate on and off resistors with dedicated diodes support user customization and optimization of on and off signals.
Common mode inductors on logic power inputs enhance EMI immunity.
Figure 8: high level block diagram of cgd15sg00d2 gate driver reference design, showing its main functional modules: optocoupler U1, gate driver IC U2 and isolated power supply x1（ Image source: Cree / wolfspeed)
summary
In power switching applications, Cree / wolfspeed's third-generation SiC MOSFET has obvious performance advantages in efficiency and heat dissipation compared with traditional Si MOSFET. When used with the right drives, they provide reliable and consistent performance for emerging and existing applications.
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