In addition, P4.2 and P4.3 of P4 portions add two external interrupts as their second function, using these two external interruptions and using P3.2 and P3.3 external interrupt methods, P4.2 (INT2) The interrupt vector inlet address is 33h, the interrupt number 6, P4.3 (int3) is 3BH, the interrupt number is 7, the external interrupt of the P4 port is connected by another newly added expansion interrupt control register. Set, see the next knowledge point.
Knowledge point: Extended Interrupt Control Register (Xicon)
The STC89 Series MCU Expansion Interrupt Control Register is CHH in the special function register, which is capable of managing the expansion interrupt, off, and interrupt priority settings. The register is all cleared when the single chip is reset. The definitions there are shown in Table 1.
PX3: Setting indicates that the external interrupt 3 is high, but the priority is finally determined by the interrupt priority register IP, the extension interrupt priority register iPh, and the extended interrupt control register Xicon, such as: [PX3H , PX3] = [0,0]; [0, 1]; [1,0]; [1, 1] represents different priorities.
EX3: Set, allow external interrupt 3 interrupt; clear 0, prohibiting external interrupt 3 interrupt.
IE3: External Interrupt 3 Interrupt Request flag, after the interrupt condition is established, IE3 = 1, the bit is automatically cleared by hardware.
When IT3: When the external interrupt 3 triggers interrupt in the falling edge; when it is 0, the interrupt is triggered at a low level.
PX2: Setting Indicates the priority of the external interrupt 2, but the priority is finally determined by the interrupt priority register IP, the extension interrupt priority register iPh, and the extended interrupt control register Xicon, PX2, PX2, as: [PX2H , PX2] = [0,0]; [0, 1]; [1,0]; [1, 1] represents different priorities.
EX2: Set 1, allow external interrupt 2 interrupt; clear 0, prohibiting external interrupt 2 interrupt.
IE2: External Interrupt 2 Interrupt Request flag, after the interrupt condition is established, IE2 = 1, the bit is automatically cleared by hardware.
When IT2: When the external interrupt 2 triggers the interrupt in the falling edge; when it is 0, the interrupt is triggered at a low level.
Knowledge point: expand interrupt priority register (iPh)
The STC89 series single-chip extension interrupt priority register is B7H in the special function register, cannot be addressed, the register and the interrupt priority register, extended interrupt control register Xicon PX3, PX2 bits to jointly decide all interrupts of the microcontroller The final priority. The register is all cleared when the single chip is reset. The definitions there are shown in Table 2.
The usage of the expansion interrupt priority register is such that if set [PX3H, PX3] = [1, 1], [PX2H, PX2] = [1, 1], the combination of other interrupts is not [1, 1] At this time, the external interrupt 3, the priority of the external interrupt 2 is higher than the other interrupt priorities, because there is no two highest, so it will look at the default priority of the system, the software settings priority level, external interrupt 2 The priority is higher. Use this method to set up any interrupt priority.
When writing a C language code using P4, add the following statement at the beginning of the program, and then operate P4 port as operating other I / O ports.
SFR P4 = 0xE8;
Note: The P4 port address of STC89LE516AD, STC89LE516X2, STC89LE58AD, STC89LE54ADR is C0H. Read more
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