"With the development of emerging applications such as 5G communication, automatic driving and Internet access, image processing, AI algorithm acceleration, software radio and other complex multi-task designs increasingly challenged the processing capabilities of embedded platforms. Special standard products can only be designers Provide unlatable fixed solutions. In this way, in order to make the design more flexible, you must add the appropriate device, so inevitably pull the BOM cost and power cost. The ZynQ-7000 SOC series of xilinx is ARM and FPGA full programmable SOC, with its flexible design and excellent performance power consumption, it is well known, but Zynq-7000 is weak compared to this SOC platform we have to introduce. It is the truly launched by Xilinx. All Programmable isomeric Treatment SOC - Zynq UltraScale + MPSOC.
Mir Technology's MYD-CZU3EG development kit is equipped with the UltraScale + MPSoc platform - XCZU3EG, which integrates quad-core CortexTM-A53 processor, dual-core CortexTM -R5 real-time processing unit and MALI-400 MP2 graphics processing unit and 16NM FinFET + The integrated heterogeneous processing system combined with high performance, low power, high expansion, etc. In addition to this heterogeneous SOC, the boards are equipped with rich interface and perfect development materials, which can help developers. Reduce the product development cycle, realize the product is fast, let's take a look at it.
Unpack
The warm colors are printed on the simple outer packaging of "Make Your Idea REAL", which is unprepared to make a hit.
After the box is set, it is placed on the board and supporting equipment. In addition to the board, a set of power, data lines, SD cards, and CDs, etc., can be described as well-equipped.
Plate resources introduction
The author can't wait to disassemble the anti-static bag of the board, let's take a look at this performance little monster. The MYD-CZU3EG development board is composed of a MyB-CZU3EG backplane by myc-czu3eg core plate. The heat sink is the core board, which is a CPU minimum system module, which integrates the main processor and storage. The bottom plate is an peripheral interface board, integrated with power and multiple interfaces, convenient to assess or integrate.
Let's take a detailed understanding of the detailed composition structure of the card, first, the core board is based on the Xilinx XCzu3EG full programmable processor, 4 core Cortex-A53 (UP TO 1.5GHz) + FPGA (154k Le), specific model: XCZU3EG-1SFVC784 (Future optional xczu2cg, xczu3cg, xczu4ev, xczu5ev), powerful performance; onboard 4GB DDR4 SDRAM (64bit, 2400MHz) and rich storage resources, calibration should be complex; onboard Gigabit Ethernet PHY and USB PHY, Easy to achieve high-speed interconnection, such a luxurious configuration, the board size is only 62 * 50mm, and the compactness is amazing.
In addition, the plate selection and materials are allegedly used, and the Intel power module, M6 PCB plate, Micron storage, and village capacitors are still very conscience.
The peripheral interface of the bottom plate is rich, and the board has served serial port, network port, HDMI, DP, SATA, PCIE, USB3.0 Type-C, LCD, PMOD, Arduino, FMC-LPC, TF card interface, SFP, ADC, CAN, etc. A variety of interfaces facilitates user assessment or integration. These interfaces are connected to the PS end according to the SOC structure, and some are connected in the PL end.
PS unit
1 channel Gigabit Ethernet
1 way USB3.0 TYPEC interface
1 channel DISPLAYPORT interface
1 PCIe2.1 X1 interface
1 road SATA3.1 interface
1 channel CAN interface
1 RS232 serial port
1 TF card interface
1 road I2C interface
1 reset button, 2 user buttons,
1 road jtag
Built-in real-time clock
PL unit
XADC interface
1 Xilinx standard LPFMC interface
1 HDMI interface, RGB 24bit, no support
1 LCD DIP / LPC interface, RGB 24bit, with HDMI multiplex display signal
Resistive capacitive touch screen interface, integrated in the LCD touch screen interface
2-way PMOD
5 power indicators
4 SFP module interface
1 Road Arduino Interface
In addition to the board, the discs in the suite provide a software development environment including the user manual, the use example, the PDF floor schematic, external expansion interface driver, BSP source package, development tool, etc., which provides a complete software development environment for developers. Product development cycle, realize the product is fast listed.
However, the current laptop has rarely with the optical drive, and copying these information, it is also true that the author has a effort. It is recommended that the manufacturer is replaced by a U disk to install information, it will be more convenient.
Zynq UltraScale + MPSOC Introduction
Real full programmable heterogeneous process SOC
Before using the board, let's take a look at the core chip of this board - xczu3eg, which is the real full programmable heterogeneous platform that Xilinx is launched after the Zynq-7000 series, Zynq® UltraScale + MPSOC device not only provides 64-bit Processor scalability, also combines real-time control with hardware and hardware engines, support graphics, video, waveforms and packet processing. On the platform containing universal real-time processors and programmable logic, three different variants include dual application processors (CG) devices, quad-core applications processors, and GPU (EG) devices, and video codec (EV) Devices, 5G wireless, next-generation ADAS and industrial network created unlimited possibilities.
The MYD-CZU3EG development kit is currently equipped with an EG device, and the CG or EV device can also be optionally available. The EG device uses a quad-core ARM® Cortex-A53 platform with a running rate of 1.5GHz and a dual-core Cortex-R5 real-time processor, MALI-400 MP2 graphics processing unit, and 16 nm FinFET + programmable logic.
The device has unparalleled integration, high performance, and low power characteristics. Compared with Zynq-7000 SoC, the system-level performance power consumption is 5 times, which is a typical application for delivery of minimum system power consumption. Including the baseband L1 acceleration, public safety and mobile radio and 8x8 100 MHz TD-LTE remote radio frequency units and other scenes.
2. Multimedia ideal system
Speaking of the application, you have to mention Zynq UltraScale + MPSOC's most good area - the frontier multimedia solution for video codec and graphics engine. Sailive SOC provides a variety of support for multimedia solutions, including:
Integrated Video Coder Unit (VCU)
Integrated Graphics Processing Unit (GPU)
Contains integrated DISPLAYPORT interface module
Integrated programmable logic (PL)
The EV device has an integrated GPU and H.264 / H.265 video codec, designed for ultra HD (UHD) video with integrated H.264 / H.265 video codec, can be coded at the same time A video of 4kx2k (60fps) can realize single-chip 4K video processing. Of course, the MYD-CZU3EG development board uses the EG device, no video codec, but there is MALI-400 MP2 GPU.
The MALI-400 MP2 GPU is directly bound to the APU, and the video graphics rendering can also be accelerated in the frame buffer, thereby implementing the display output. The GPU can be rendered by a separate parallel engine, which is much higher than relying on the CPU to handle graphics, and the cost and power consumption is lower than the solution that requires the designer's additional GPU engine. The GPU accelerates 2D and 3D graphics through a comprehensive programmable architecture, which supports both shadlor-based graphics APIs, also supports fixed-function graphics APIs. The GPU has anti-aliasing function, achieving optimal image quality, and hardly resulting in additional performance loss. Xilinx supports a full set of Linux drivers that use practical tests that automatically turn the graphic command from the APU to the CPU processing.
In addition, Zynq UltraScale + MPSOC provides high-speed interconnect, which contains an integrated DISPLAYPORT interface module. The DISPLAYPORT interface is located in the PS side, which can be multiplexed to two of the four dedicated high-speed serial transceivers, with a working rate of up to 6 GB / s. The architecture gets rid of the need for additional display chips, further reduces the system BOM cost.
The DisplayPort interface is based on VESA DISPLAYPORT Standard Version 1 and Revision 2A, which provides multiple interfaces that can process real-time audio and video streams from PS or PL, and can also store audio and video from memory frame cache. It also supports two audio and video lines, supports dynamic rendering of ALPHA mixing, chroma complex, color spatial conversion, and audio mixing. DisplayPort can either a PS PLL that generates a pixel clock using a PL clock.
In addition to video codecs and graphics processing, multimedia applications also require other important components, such as input and output management of video data, and to process high-speed video data. Customized logic can be designed within PL to capture video from live sources. For example, protocols such as SDI RX, HDMI RX, MIPI CSI IP can be used to capture raw video from different sources. Visual algorithms can be used to collect important information from raw data, such as roadpit recognition, and action detection for driver auxiliary techniques, video monitoring facial identification, objects and action identification of advanced shooting applications. In addition to collecting data, the algorithm can also be used in the use cases of audio and video broadcasting and video conferencing. Considering the inevitational trend of video resolution in the next few years, the algorithm requires extremely high working speed. PL provides the hardware acceleration feature required for such algorithms, making it greatly to improve performance to meet the next generation of technical needs.
The Flexibility of Zynq UltraScale + MPSOC Accelerates the calculation of the intensive application, shares the workload between the GPU, CPU, and PL, uninstall complex calculation calculations in the PL to achieve hardware acceleration, and pre-calculate OpenGl coloring language in APU ( GLSL) unanimous variable. The calculation on the GPU shader core is only available for different values between vertices and pieces. All the values of all maintain constants in the vertex are most effective on the CPU.
3. Unparalleled system performance power consumption ratio
Zynq UltraScale + MPSOC considers high-efficiency power management issues at first, which is divided into four power domains:
The battery power field in the processing system (PS) contains real-time clocks and battery powered RAM.
The low power field in the PS contains RPUs, universal peripherals, on-chip memory (OCM), platform management units, and configuration security units.
The full power field in the PS contains APU, high speed peripherals, system memory managers, and DDR controllers.
Programmable logic (PL) is located in its own power domain
Zynq UltraScale + MPSOC contains an innovative platform management unit (PMU) that controls power domain. PMU is responsible for the safety management of the device and regulating power in the power domain. Unshaped power domains can be turned off at startup, then smart from interruption or event wake up to achieve fine power management.
We already know that the Zynq UltraScale + MPSOC has multiple processing cores. The quad-core ARM Cortex-A53 is an application processing unit, which has an efficient baseline performance, suitable for Linux application processing; dual-core ARM Cortex-R5 is the real-time processing unit ideal for low-time Deferness applications, such as security modules and APU task sharing, etc., additional graphics engines, high-speed peripherals, etc. Optimized for specific applications, and all modules, system performance is significantly improved. The device uses a 16nm FinFET process node of TSMC. The process node uses a more efficient transistor implementation, with optimal switching speed and leakage current lower than planar processes, thus achieving higher performance and lower power consumption. From 28 nm Zynq-7000 to 16 nm Zynq UltraScale + MPSOC, performance has increased by 60%, and the power consumption is reduced by 20% to increase the original processor performance by 2.7 times.
Example
The board QSPI flash memory pre-burned Linux mirror, the default is started from QSPI flash, using the data cable to connect the board serial port and PC, connect the power, board power, open the power, and open the system startup information. You can log in by the command line, the default password is root.
The system's mirror file is also provided. If the user is not familiar with the Linux system compile, it can be used directly.
In addition, a demo program for common peripherals is provided in the MYD-CZU3EG disc, for example:
Use the LINUX API to operate the LED on the development board
Use the Linux API to operate the button on the development board
Use the Linux API to operate the CAN on the development board
Network communication using the Linux API
The program and source code are located in "
/ example /", and the user can compile according to Makefile within the directory.
Here we use Xilinx Vivado to create a new HelloWorld project to generate a launch mirror, start from the TF card. The whole process is divided into:
Hardware platform for generating development board
Export hardware platform to SDK
Create a "helloworld"project
Generate Boot Loader (FSBL)
Generate an SD card startup image, start from MicroSD
The following is the process of actual operation:
(1) New VIVADO project
Create an RTL project, choose the development board chip to XCZU3EG-SFVC784-1-E.
(2) Create block design, add and configure the IP core of PS
Click IP Integrator-> Create Block Design to create a new block design, click Add IP,
Add Zynq UltraScale + MPSOC IP core
Double-click Zynq MPSOC Nuclear Import Profile Presets -> Apply Configuration
The manufacturer provides an example pre-profile in the disc data, imports the Hello_World.TCL configuration file, then click OK.
(3) Generate a comprehensive file
Right click on Design_1-> Generate Ouput Products-> Generate
(4) Generate the top layer file of the FPGA
(5) Generate BitStream
(6) Export hardware profile
Click on the file-> export-> export hardware-> OK on the menu bar to export hardware profiles
(7) Start SDK, new FSBL
Click on the file-> launch sdk-> ok on the menu bar to boot SDK
In the Xilinx SDK software, click File -> Application Project New Project, enter the project name FSBL, select Zynq MP FSBL, click Finish.
(8) New HelloWorld Project
Click File -> Application Project in Xilinx SDK, enter the project name Hello_World, select Board Support Package for the FSBL_BSP generated in the previous step, select the Hello_World template, click Finish.
(9) Generate Boot Image
Right-click Hello_World -> CREATE BOOT Image, click Create Image to generate boot.bin boot files
Putting the startup mode SWITCH switch SW1 of the development board to OFF, 2 to ON, 3 to OFF,
4 Dial to ON, set to TF card startup mode,
The Boot.bin file is then copied to the SD card, the board is connected to the power supply, the serial port is connected to the computer, turn on the power switch, and run it on the development board. The computer is connected to the microusb line, opens PUTTY, can run on the board on the terminal print character "" Hello World "
Summarize
As the first Zynq UltraScale + MPSoc platform development board, MYD-CZU3EG core plate performance configuration is powerful and the design is compact and reliable, the peripheral bottom plate is rich, and the software development environment provided by the manufacturer provides for the developer is also relatively perfect, which is very suitable for artificial intelligence, industry Control, embedded visual, ADAS, algorithm acceleration, cloud computing, cable / wireless communication, etc. are developed.
Be
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