"Background
In the past few years, many small electronic product research and development companies rely on one or two sets of embedded MCU hardware design, with different products that have changed or add various functions in the case where the hardware performance is not large, and the different products are formed by changing or adding various functions. The market is mixed on the market, although there are still many companies, but as the market competition is more fierce and diverse, in the face of the more and more powerful, more and more emphasized electronic products, This kind of "one stroke is full of fresh" is a bit of weak. Many previous embedded MCU hardware solutions may not meet the design of existing products in terms of performance, function, IO, etc., this time, either select performance. The more powerful MCU scheme (may replace the MCU platform), or increase the IO expansion chip, but these programs can be said that it is only temporarily solved the problem in front of you, and it may need a new round of replacement. Although this is also a common phenomenon in the industry, is there a solution to at least delay this change, which can greatly reduce the development costs and energy caused by frequent replacement hardware platforms, saving project development cycles?
There is definitely, for example, FPGA, but there is currently a variety of FPGAs on the market, how should I choose? Recently, the pavilion has got a new FPGA entry suite from Lattice. Based on the latest MachXO3LF devices, not only embeds the FLASH module, integrated FPGA and CPLD, but also starts on instantly, no need to reconfigure FPGA from the outside. And integrated high-speed I / O, you can easily implement MIPI D-PHY, CSI-2 or DSI interface bridge, if you just have this demand, continue reading this article, Lattice's MachXO3LF device can not only let you keep the original design And only one-time investment, don't say you can hold a two decade, but at least you can keep up with the changing market through flexibility in five or six years.
Lattice Machxo3LF Starter Kit
Lattice's Machxo3LF Starter Kit is looking at the word "Getting Started", it is really simple, whether it is a packaging or development kit itself.
The kit contains a MachxO3LF Starter Kit, a miniusb cable and 4 rubber pin.
The MachxO3LF entry kit is an underlying branchboard (you can understand like the MCU minimum system board), size is 76mm * 76mm, with 1 USB Mini-B connector available for power supply and programming, 1 LED array and The experimental test area can be used to make simple assessments and development based on the design of MachXO3LF devices, although it is simple, but the corresponding is very flexible, users can free DIY.
MachxO3LF Kit Hardware Interface Schematic block diagram is as follows:
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Specifically to understand some of the resources and interface situations, as shown below, similar to the minimum system board of microcontrollers we usually contact, the MachxO3LF entry suite only reserved some extension interfaces, but it is worthy of the card. Mounted onboard programmers, eliminating users' development costs for users to buy, you can play.
With a SPI flash over the back of the board, it can be used to evaluate the external start or dual start function of the FPGA.
The main features of the MachxO3LF entry suite include:
Machx03 FPGA - LCMXO3LF-6900C-5BG256C
USB Mini-B interface for power supply and programming
8 LEDs, a power indicator
4 Dip bit DIP switch, a mechanical button
40 "cave" interface prototype area
4 2 * 20 IO expansion interface, JTAG interface, external power interface
An 8PIN extension interface for JTAG
A 6PIN extension interface for SPI / I2C
3.3V or 1.2V power supply
Lattice LCMXO3 FPGA
Key to see the core FPGA device LCMXO3LF-6900C-5BG256C on the MachxO3LF development kit, which is a FPGA chip for bridge and extending the IO port of Lattice.
From the Lattice official website, it can be learned that the FPGA device mounted on the suite belongs to a higher-specific product in the Machxo3 series, with 6900 logic units, with 256 foot Cabga packages, which are shown in the following table.
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The Lattice Iceblink40-LP1K Evaluation Board is a solution designed for sensor management, video, and images, custom connection and memory / storage extensions.
MachXO3 products are divided into six products according to different logical resources and functions, each product is divided into devices embedded Flash modules or embedded NVCM modules, where the author picks several MachXO3 important features.
Inline Flash or embedding NVCM module
According to the name of this FPGA model, the author is a product that belongs to the embedd Flash module. If the benefits don't have to be said, no external configuration, start-up instantaneous start, allowing FPGA to achieve more reliable systems and implementations The function of the system is functional, in addition, from another aspect, to provide better protection to prevent intrusion and other security threats with physical properties of such FPGAs in burying Flash.
Of course, it is advantageous to have a disadvantage, that is, the price, power consumption, usually the FPGA of the embedded FLAHS module will be higher in price and power. It may also be because of this factor, we have seen another product LCMXO3L in the Lattice product line, seeing a difference from naming, that is, remove the embedded flash module, and the embedded NCVM module. NCVM is also non-volatile configuration memory, which is a large number of techniques that use and verified in ICE FPGA, which is used to replace embedded flash, and ensure maximum programmable characteristics that guarantees low cost, important It is also costly, but also reduces static and dynamic power consumption. Of course, there is also a good news for engineers. The LCMXO3L and LCMXO3LF series are Pin-to-PiN compatible, seamlessly portable.
In general, MachXO3LF embedded flash, which can have a shorter FPGA configuration time, but cost and power consumption, and MachXO3L embedded NVCM, lower power consumption, more flexible, but consider going to external Flash Used, the FPGA configuration time is longer.
Support MIPI D-PHY
I don't think you will be, after all, the current smartphone, the tablet, etc. are all components of the MIPI interface. However, in the case of it, this is simply providing a powerful support for a flexible support for the change of the current type of embedded system solution. I still remember that the article said that many electronic products want to increase the highly popularity of the mobile platform, the cost-effective components, the existing hardware solution does not support, especially in the display, cameras Device. Suitable for mobile platforms, unified low-cost MIPI standard components use D-PHY physical bus interfaces, unable to connect the display of the display using LVDS, RGB or SPI interfaces, and embedded system processors connected to image sensors through digital parallel interfaces. Communication. At this time, the Lattice MachxO3LF series of MIPI D-PHY is supported by the land.
At present, the mainstream, low-cost MPI CSI-2 (camera interface) and DSI (display interface) interface are D-PHY physical bus protocols, and if the dedicated ASIC chip is bridged, it is not only expensive, the development cycle is long, but also Not flexible, once the type is difficult to support such design changes, if the Lattice Machxo3 FPGA is used to build bridge, the advantage is highlighted, and it is highly configurable. The second is direct pain points, support MIPI D-PHY Of course, users are more concerned about how to build, so that Lattice seems to take into account these situations, there have been many reference designs for MIPI displays and camera applications, as shown below:
For the DSI display, the MIPI DSI transmission bridge of the Drive DSI receiver
Connect the application processor to the DSI reception bridge that is not a display of the display design for mobile applications
Connect the application processor to the CSI-2 transmission bridge of the non-CSI-2 image sensor
Connect the CSI-2 image sensor to the CSI-2 receiving bridge of embedded ISP
The specific content of the application will not be elaborated in this article, and the engineers who have an urgent needs have quickly contacted the official to obtain these information.
We all understand that today's embedded system markets, developers are exhaustive means compressed system costs to the lowest, control the size and power consumption to the lowest, and currently boost MIPI interface The very cost-effective MIPI interface components brought by the smartphone are not the material preferred by the engineer. With the Lattice's programmable bridge, use the MIPI interface display, camera, application processor's advantages to reduce system cost Hele Not.
Development environment
Each FPGA vendor has its own EDA tool. It has known the importance of the EDA tool for FPGA using programmable device, so it is also possible to affect the company's FPGA product attitude towards this company. Lattice's own EDA tools are Diamond, support Windows32, 64-bit, and Linux 32-bit, 64-bit systems, more powerful, we can go directly to the Lattice official website to download for installation, which is very convenient. (Diamond installation package download address)
An optional installation component is displayed during the installation process, and it is installed by default.
When you need to choose from to where License activation, select Node-Lock Licnse, Lincense can be obtained free of charge.
After the installation is complete, you should copy the licensed license to the Diamond installation directory. Under the Diamond installation directory, set the environment variable to the correct address, you can open the Diamond tool after completion, the picture below shows the interface of the Diamond tool, looks very simple, On the right side of the software window is a large number of document links such as User Guides, Reference Guides, Tutorials, FPGA Design Guide, which is guided.
FPGA related development board wonderful recommendation:
The Basys 3 Artix-7 FPGA board is an entry-level FPGA board with the Xilinx Artix 7 FPGA architecture for the Vivado design kit.
TERASIC DE0-NANO-SOC Development Suite A new dual-core ARM® CortexTM -A9 embedded kernel combines with industry-leading programmable logic devices.
The Lattice Iceblink40-LP1K Evaluation Board is a solution designed for sensor management, video, and images, custom connection and memory / storage extensions.
Power-on start
The MINIUSB cable comes with the MachxO3LF kit can be powered directly on the board. The board is programmed by the onboard FTDI USB to serial port chip, usually, when Diamond is installed, automatically recognizes the programming module. If you do not automatically install the driver, you need to download the driver first, download the driver version according to different systems (driver download address).
The MachxO3LF kit has been prepared for a demo Demo. After power-on, you can see the running status of Demo directly.
Demo's source program can be found in the Lattice website, mainly explaining how to use the MachXO3LF oscillator and programmable IO to configure the drive LED.
Download the program that completed the compilation to the development board, select Tools -> Programmer, select the correct download cable
Download completion will have a prompt to prompt Pass.
Relatively speaking, Lattice's Diamond EDA tool will feel very simple, and the execution efficiency is relatively high, if you are interested in Lattice's Diamond, you want to know more to refer to the patriarid network forum About the little foot FPGA Diamond The EDA tool uses the tutorial, there is more detailed, step by step, how to use it, the article is more introduced to the operation of the Diamond tool.
In addition, the second generation of FPGA development boards has also been sold in the pavilion mall, which is still using the Lattice MachXO2 series FPGA, which is only 52mm x 18mm, but the logic resource of the FPGA chip on the board is improved. 4 times; simultaneous board integrates FT232 programmers and buttons, DIP switches, digital tubes, LEDs and other peripheral resources; 36 FPGA IO interfaces on the board are drawn from 2.54mm through-hole pads, and Bread board works,Live embedded socket or other systems.
Small knot
Introduced the Machxo3 series of FPGA development boards launched by Lattice, the board reserved a number of extension IOs, with a board programmer, which can easily develop and free DIY. The Lattice Machxo3 product inherits the embedded Flash of Machxo2, and expands the embedded NVCM product line, which is convenient for engineers in the product design. The most unique is that MachXO3 supports MIPI D-PHY, combined with Lattice Bridge application reference design, you can make mainstream MIPI interface display, camera such as the camera to existing embedded system design, greatly reduced the cost of the entire system.
FPGA related development board wonderful recommendation:
The Basys 3 Artix-7 FPGA board is an entry-level FPGA board with the Xilinx Artix 7 FPGA architecture for the Vivado design kit.
TERASIC DE0-NANO-SOC Development Suite A new dual-core ARM® CortexTM -A9 embedded kernel combines with industry-leading programmable logic devices.
The Lattice Iceblink40-LP1K Evaluation Board is a solution designed for sensor management, video, and images, custom connection and memory / storage extensions.
Reference
Machxo3 FPGA Product Information
Machxo2 FPGA Development Board
Diamond EDA Tools Download
Lattice Diamond EDA Tool User Guide
Original declaration: This article is originally created by the panel network, declined! "
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