In some fields of measurement and control, the A / D converter is required to have multi-channel simultaneous tracking / hold (T / H) function to eliminate the difference between the source sampling time. The MaxL55 / MaxL56A / D converter launched by US Maxim is a typical one. The MaxL55 / MaxL56A / D converter has its own T / H, and all T / h samples at the same time, MaxL55 / The MAXL56A / D converter also has a 2.5V internal reference and power shutdown function to provide a complete data acquisition system, combined with the use of the chip in the radar high-frequency transmission system monitoring device, this article will be MAXL55 / 156 Simple introduction of the structure, functional characteristics and its working principle.
1 MAXL55 / MAXL56 overall structure and main features
MaxL55 / MAXL56 is a high-speed, multi-channel 8-bit analog-to-digital converter (ADC), and MaxL55 has 8 analog input channels, and the MAX156 has four analog input channels. Every channel has its own T / H to sample the same time. The converter is converted over a channel in 3.6 μs and stores the result in the 8x8RAM in the tablet. When working in a single power source of + 5V, the MAXL55 / MAXL56 can operate in unipolar or bipolar, single-ended or differential conversion. The internal structure is shown in Figure 1.
MAXL55 has 28 feet DIP packages and width SO packages as shown in Figure 2, MaxL56 has 24 foot narrow plastic DIP and 28 foot width SO package.
2 MaxL55 / MaxL56 pin description
3 MaxL55 / MAXL56 basic working principle
The MAXL55 / MAXL56 contains a 3.6μs sequential comparison ADC and 8/4 tracking and holding input. When the conversion begins, all AIN is simultaneously sampled. Whether each channel is sampled depends on whether they are selected. A single-channel or multi-channel conversion requires a pre-request and the channel can be a single-ended and differential mixing. The result of the ADC is saved in the slice.
A WR pulse is given, the rising edge of WR, MUX configuration register data; in the falling edge of WR, all input starts to sample. The access conversion result is to automatically access the RAM from the channel 0 started with a continuous RD pulse. Each RD pulse adds the RAM address counter plus 1. In multi-channel conversion, when WR becomes low, the RAM address counter is reset to 0. On the load RAM address (A0 to A2), the D4 / INH is 1, the address can be set and the conversion is prohibited, and then one read operation can be read, either the address of the RAM can be read.
4 MAXL55 / MAXL56 interface timing
When the MODE input port is open, it is a soft configuration mode. In soft configuration mode, the MUX configuration register determines the type of conversion. In the rising edge of WR, the register is updated. After the start of the conversion, the BUSY end is low, and the conversion is in order from the selected minimum channel. When BUSY becomes high, the conversion result is stored in the RAM. After the conversion is over, the microprocessor can access data in the RAM with a continuous RD pulse. The first read data is the conversion result of the lowest channel, and the subsequent pulse sequence reads out the residual result of the remaining channel.
For more simple applications, the connection between the MODE and VSS ends can be used to specify the type of conversion, as shown in Table 2. In this mode, the configuration register is not used, so the input data of the D0 to D7 is ignored. For example, the MODE is connected to a low level. Under WR pulse, the single-ended conversion of the 8-channel will be activated; the MODE is connected to a high level, and the 4 channel differential conversion is activated under WR pulse. Data appearing in DO to D7 does not affect the configuration register.
5 MAXL55 / MAXL56 Application in Radar High Frequency Transport System
The radar high-frequency transmission system is connected between the transmitter, the receiver, and the antenna, which is an important part of the entire transceiver system. It mainly assumes that the high-power high-frequency energy generated by the transmitter is smoothly and efficient, and the antenna will Weak signal feeds to the function of the receiver. Therefore, his working condition is directly related to the performance of the transmission and reception system and even the overall radar. Since the system works in high-power high frequency, the relevant device is easily damaged (loss) effect, causing system main performance indicators to reach the requirements, so that the high-frequency energy cannot be effectively transmitted, leaking power exceeds the standard, resulting in a chain reaction, resulting in a chain reaction Related devices are damaged or burnt. Not only is the economic loss, but also makes the entire system work properly. In order to avoid the occurrence of the above situation, the high-frequency transmission system monitoring protection device can be improved by implementing a quantitative real-time monitoring and security in the system of related devices in the system, it can greatly improve the targeted and effectiveness of maintenance support work. Fundamentally change the current backward monitoring means to make radar security levels and capabilities produce a quality leap. Figure 3 is a system configuration diagram.
In the radar high frequency transmission monitoring device, a sample signal is obtained from a dedicated sensor, and the voltage input range of the pre-processing circuit reaches the voltage input range of the A / D converter, and the single-chip microcomputer is obtained by obtaining the A / D converter. The average value of each peak detection is displayed by the single-chip drive, and when the transmission system fails, the single-chip call is called alarm program. If the three-lasting sample value exceeds limit, the sound and light alarm and drive the transmitter high pressure protection. Circuit. It can be seen that the system has high requirements for the multi-channel T / H function of the A / D converter, so we adopted the US MaxL55 / MaxL56A / D converter.
Using the MAXL55 MODE end, VSS picks up a 5V 8-channel mode sample, and MCS-51 gives a WR pulse, starting at the falling edge conversion of WR, at which time the ADC's RAM address counter is reset to 0, after the conversion ends, The MCS-51 reads out the data in the RAM by a continuous RD pulse order. The conversion result of the minimum channel is read, and the subsequent RD pulse sequentially reads out the residual result of the remaining channel. Figure 4 shows the interface circuit diagram of the MAXL55 and the MCS-8051.
Several problems that should be noted in 6 applications
The inside 2.5V base source output (REFOUT) must pass by 1 4.7 μF electrolytic capacitance and 1 0.1μF-free capacitor, and if the input signal is lower than the ground level, negative must be used. Power supply to ensure the stability of the device.
If REFOUT must be connected to the REFOUT to prevent the REFOUT to prevent the oscillation output from the ADC, but the disadvantage is that the disadvantage is in the power shutdown mode. The current will give a value of 250μA.
The input impedance of the MAXL55 / MAXL56 T / H amplifier is high, and it is generally not required to input buffers. MAXL55 / MAXL56 all T / H simultaneously sampled. In order to get the best results, the analog input should not be higher than VDD + 50mV or lower than VSS one 50mV. The time required for T / H collects input signals required, depending on the speed of the channel input capacitor charging. If the source impedance of the input signal is high, the acquisition time is long, the interval between the two conversions should be longer, and the acquisition time is generally not less than 800ns.
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