Sampling Circuit Principle (S / H)

Principle of sample and hold circuit (s / h) A / D conversion takes some time. During the conversion process, if the analog quantity sent to ADC changes, the accuracy cannot be guaranteed. To this end, a sample and hold circuit is added before the ADC, as shown in Figure 8-30. The sample and hold circuit has two working states: sample state and hold state. Sampling status: the control switch K is closed, and the output changes with the input. Keep status: Adc1210 is an A / D converter without three state output latch function. As shown in Figure 8-28, it is a 12 bit successive approximation ADC with conversion time of 100 microseconds. Its data line cannot be directly connected with the system data bus. It must be connected to the data bus through two 74ls244 with three state latch capability, as shown in Figure 8-29. Where: D11 ～ d0: data output line. The data result is binary inverse code. The output has latch but no three state function. A three state buffer (74ls244) shall be added to the interface circuit. SC: start signal. For pulse start, the width of SC is required to be equal to the clock cycle, and the "NAND gate RS trigger" is used to ensure synchronization with the clock signal. CC: conversion end signal. The low level is active until the next start of the conversion Adc570 overview ad570 is an 8-bit successive comparison ADC started with level, with conversion time of 25 μ s. Accuracy ± 2lsb. The chip contains: D / a conversion circuit, clock pulse, comparator, successive approximation register, SAR and buffer register. Its pins are shown in Figure 8-25. DB7 ~ db0: data output line. There is a three state buffer register inside ad570, but the register is not externally controllable. At the end of a / D conversion, the register is automatically connected. There is always signal output on the data output line before the CPU reads the data. Therefore, an additional externally controllable three state buffer should be designed in the interface circuit, which is gated only when the CPU reads data. Ain: analog input. Single ended. It can be unipolar or bipolar. It is selected by 15 pin BOF (bipolar off): BOF grounding; Unipolar, input range 0 ~ + 10V. BOF is suspended; Bipolar, input range - 5V ~ + 5V. B / C: start signal (blank / conv). Level start. Dr: conversion end signal (data ready, technical zone) Medical grade market becomes a new profit engine ADI covers two major fields of medical care Discussion on the components of output noise Solutions to 82 difficult problems in high speed AD / DAC measurement and design How to design the system input and output protection circuit? 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