"By Mike Santarini Publisher of Xilinx China Communication magazine
Over the past 40 years, the rapid development of IC process technology has driven electronic enterprises to launch rich products for today's people to enjoy. However, the development of chip technology is very important for electronic innovation. Without the support of academia and electronic design automation (EDA) industry, chip technology can not develop so smoothly. From the transistor level SPICE simulation in the 1970s to today's billions of gate system level integrated design environment, such progress is really rapid. However, the design methods that have made great contributions to the innovation of electronic technology are also amazing, but they are often ignored.
The design team can use the world's most advanced chips and the best tools, but if they can't establish an effective design method, they can't launch products in the right time, and it's difficult to achieve commercial success. A good design method can not only shorten the design time and enable the design team to deliver high-quality products on time, but also enable them to work in a predictable and repeatable way, which is the key to long-term business success. In this regard, the design method should be continuously developed and improved to give full play to the improvement of chips and design tools.
Convergence from the front of the design process
– accelerate iteration
– greater impact on the quality of results (QOR)
Shorten the design time and reduce the design cost
Figure 1: convergence at the beginning of the process can greatly improve the quality of results and shorten the design time
In order to help customers further improve productivity and successfully realize a new generation of innovative technologies, Xilinx aims at its award-winning vivado ® Design Suite introduces ultrafast ™ Design method to help the design team using vivado accelerate the development of Xilinx 28nm 7 series devices and the upcoming 20nm / 16nm utrascale ™ Successfully implemented the design on the product series.
Ramine Roane, senior product marketing director of vivado design suite, pointed out that this new design method is not a completely separate portal, but the company selects several best examples according to the suggestions of industry experts and simplifies them into a set of effective methods to promote the design team towards predictable success. This method is collectively referred to as ultrafast design method. These best examples cover development board planning, design creation, design implementation and convergence, programming and hardware debugging.
Roane pointed out: "the ultrafast design method will help the design team make full use of the advanced technology of vivado design suite and Xilinx all programmable devices to improve productivity, continuously shorten the design time, accurately predict the design progress, and then accelerate the product launch process."
The introduction of ultrafast design method is another example of how Xilinx keeps ahead of its competitors for a whole generation. Xilinx not only introduces the best devices and the most advanced tool kit, but also provides the most comprehensive design method in the industry.
In order to accelerate the promotion of utrafast design method, Xilinx has issued a free design method manual ultrafast design method guide of vivado Design Suite (ug949) to help readers understand the design method step by step, including the selection of development board, RTL design, implementation and final debugging. The manual provides a comprehensive checklist to guide engineers to complete the whole design process. In addition, vivado Design Suite 2013.3 also automates many elements of design methods (including linking) and adds new design rule checks (DRC rule decks), entitled "methodology" and "timing".
The new vivado design suite also provides hardware description language (HDL) and Xilinx design constraints (Xdc) templates to help optimize the quality of results (QOR) of synthesis and implementation. Xilinx also offers a series of free online self-study videos and official training courses in different regions of the world.
Design method of accelerating convergence
Roane pointed out that the main purpose of ultrafast design method is to bring design convergence to the front end of the design process, which is also where QOR has a great impact (see Figure 1). In this way, the design team can quickly form a "correct by construction" design scheme. "If we can fully understand the situation and make decisions in the early stage of the design process, we can effectively avoid taking too long in the implementation stage," Roane said
Roane pointed out that vivado design suite is the only design suite in the programmable industry that supports interactive design analysis and source file cross detection in every link of the process (from design input to IP integration, RTL synthesis, implementation (optimization, layout, physical optimization, cabling) and even startup). Roane said: "when using traditional tools, designers can only find problems at the end of the design process and after the full implementation of the planning. If the design scheme can not achieve the expected effect, the only way is to start from scratch, and they don't know the cause of the problem at all, so they have to carry out many long-time iterative cycles."
The main factor to realize the cross detection and analysis function is the unified data model of vivado design suite. "The unified data model enables the design team to adopt the same analysis and convergence procedures throughout the process," Roane said. This is a big advantage over the old design suite. It can help engineers modify the design scheme in multiple links (even in the temporary memory where the design changes have not been saved), and cross detect the source file or other design views. The unified data model designed by Xilinx can be extended to high-end devices with millions of logic units, and similar competitive tools are just beginning to meet the requirements of middle-end devices. "
Perhaps the best example that can reflect the ultrafast design method to accelerate design convergence is the concept of "baseline".
Fast timing convergence through baselining
"Baselining is a technology used to accelerate design convergence. It focuses on solving the internal Fmax, which is the biggest problem. It is the problem of 9 times of convergence in 10 times. This can avoid time delay due to complex and error prone I / O constraints and timing exceptions, and prevent users and tools from being guided in the wrong direction. Using baseline technology, the design team can start the convergence process with the simplest constraints and focus on the trigger path. Then, depending on whether the problem is in the clock path or data path, connection delay or logical delay, we can take documented modification measures and rerun the analysis. "
Once the design team converges the timing with baseline Xdc, it is basically completed. Then you need to add I / O interface constraints. "The correctness of these constraints must be ensured to avoid 'false' timing problems," Roane said
"Because of this, we provide Xdc templates for source synchronization, intermediate aligned DDR I / O constraints, etc. If necessary, we can use special timing cases to fine tune constraints or carry out certain layout planning. However, it is important to remember that if the corresponding path is not a critical path, it is best not to use a timing exception. Similarly, excessive design and layout planning cause more problems than they do. "
Roane pointed out that the baseline method can not replace the sign off constraint: "the design scheme still needs to be verified on the basis of complete constraints."
The ultrafast design method also provides detailed steps to obtain the original signing constraints. Vivado automates this task through a large number of batch processing and graphical interface programs, and analyzes the timing path, clock network, interaction between clocks, etc. The new timing DRC rules can also be used to check the design constraints and clock networks.
Ultrafast design method of vivado Design Suite
Baselining: a technique for rapid design convergence
Baseline Xdc
All Xdc
Sign-off XDC
(internal Fmax)
(including I / O)
All constraints
Use exceptions, layout plans only when needed
Figure 2: baseline method helps the design team achieve timing convergence quickly.
To become familiar with the ultrafast design methodology, start by reading the ultrafast design methodology guide for vivado design suite. The guide is divided into six chapters. The first two chapters introduce the contents and design process suggestions of the guide, and chapters 3 to 6 deeply analyze the best practices of ultrafast design methods.
The third chapter analyzes the development board and device planning, and gives wise suggestions on PCB layout, clock resource planning and allocation, I / O planning and design process, FPGA power consumption factors and system dependence. In order to avoid the revision of the development board, this design method briefly introduces how to use Xilinx power estimator (XPE) to explore and find an architecture that meets the requirements of power budget allocation.
This chapter also emphasizes the importance of starting design with good I / O planning, and gives suggestions on I / O planning in cooperation with development board planning. At least the two should be properly coordinated. If I / O planning and development board planning are not coordinated, system level timing and power distribution problems will occur in the later stage of the process. This chapter also discusses various power consumption modes, gives suggestions on power and heat dissipation analysis, and introduces the refrigeration considerations of PCB. In addition, this chapter also gives relevant I / O suggestions for the implementation of Xilinx all programmable 3D IC in the design project, because the inserter connecting multichip devices has unique requirements.
The fourth chapter "design creation" first introduces the strategies and skills of creating a reliable design level and selecting an appropriate IP. The next few parts introduce a practical RTL coding guide. This chapter also covers control signals and sets, ram and ROM inference, code forming correct DSP and arithmetic inference, shift register and delay line coding, and initialization of all inferred registers, SRL and memory. This chapter also includes "parameters, attributes and constraints", "clock" and "selection of instantiation and inference methods".
"The way HDL is written has a great impact on how to synthesize reasoning logic. Good coding style makes the design use the inherent resources in the architecture, so as to improve the working frequency. "
Roane pointed out: "the way HDL is written has a great impact on how synthesis infers logic. Good coding style makes the design use the inherent resources in the architecture, so as to improve the working frequency. To help customers make full use of these resources and accelerate the overall design process, we provide templates to guide the reasoning of these components, especially the use of ram, shift register and DSP resources. These templates are built into vivado Design Suite version 2013.3. "
This chapter is also divided into three sections, focusing on the coding technologies to improve reliability, performance and power consumption optimization. Each section gives constraint suggestions to give full play to the advantages of the unified data model of vivado design suite.
The section "coding style for high reliability" gives suggestions on clock domain crossing (synchronous and asynchronous), unconstrained reset and avoiding combinational logic loop“ The section "coding style to improve performance" gives suggestions on high fan out and register replication on critical path, as well as matters needing attention in the implementation of pipeline in design“ The section "coding style for optimizing power consumption" introduces a variety of different power saving technologies you may use in your design, including proven and reliable methods such as data path and gating clock, as well as some subtle suggestions such as maximizing gating elements and limiting control signals.
The fifth chapter focuses on the whole implementation process from generic cabling to cabling. This chapter first summarizes the advantages of implementation, comprehensive attributes and bottom-up design process. As mentioned earlier, this chapter deeply introduces time series analysis and gives the baseline method concept of time series convergence. In addition, the timing convergence section also gives good suggestions on what to do and what not to do in the face of various timing problems. This chapter also discusses the possible impact of timing on power consumption.
The last chapter of this guide, Chapter 6, covers configuration and debugging issues. The first half of this chapter leads the reader step by step to the best way to generate bitstreams and configure Xilinx all programmable devices. The second half mainly introduces the best practices of multi-stage debugging design in the design process. This part discusses how to implement HDL instantiation debugging probe point process and how to insert debugging probe point process in netlist. This chapter also discusses the design and debugging strategy after the design is loaded into the target device.
The appendix of this guide gives more rich resources. Perhaps the most important resource is the ultrafast design method checklist, which lists the matters that the design team should consider at each stage of the design cycle, from the initial design planning to the final hardware debugging. "It gives a long list of questions, highlighting typical aspects of design decisions that may affect downstream processes," Roane said The checklist not only allows readers to link to the relevant aspects of the guide, but also provides external links to specific design issues. Xilinx's checklist also provides downloadable spreadsheets.
Support for ultra fast design methodology
In addition to compiling all best practices into the extremely useful guide to ultrafast design methods of vivado design suite, Xilinx has also integrated many suggestions on ultrafast design methods in vivado Design Suite 2013.3. Vivado Design Suite 2013.3 currently supports ultrafast design method and timing DRC rules, which can better guide users to complete design work step by step, and provides very convenient hardware description language (HDL) and constraint template to support automatic construction and correction.
In addition, Xilinx's global trainers and alliance member ecosystems are actively supporting the use of ultrafast design methods.
For example, blue pearl software added Xilinx ultrafast design rules to its analyze RTL linking tool. Roane pointed out: "Blue Pearl automates the RTL guidelines in the ultrafast design method. In addition to the execution language linting, it also forces the use of specific coding styles to ensure the best result quality of Xilinx devices, including the use of appropriate reset types, ram or Mac coding methods to best infer the built-in inherent modules of Xilinx devices. "
In addition to the third-party EDA support, Xilinx also actively tests its IP core to ensure that it meets the ultrafast method and DRC requirements, and actively encourages all IP manufacturers of alliance members to also ensure compliance with the guidelines.
Last but not least, Xilinx is launching Xilinx and its global partners
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